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AR# 24955

ML505 - ML505 ZBT SRAM clock signal integrity issue

Description

Intermittent failures with ZBT memory are attributed to a non-optimal signal integrity on sram_clk pin in the UCF file.

Solution

Update the ML505 UCF as follows:

Change NET sram_clk IOSTANDARD as follows:

From:

NET sram_clk IOSTANDARD = LVDCI33 ;

To:

NET sram_clk IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;

NOTE: For other ML505 board issues, perform an Answer Record search for ML505.

This problem has been fixed in the latest EDK 9.1i Service Pack, available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 9.1i Service Pack 1.

AR# 24955
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article