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AR# 24956

ML505 - How do I meet timing for the ML505 reference design in the ISE 9.1i Design Tools?

Description

How do I meet timing for the ML505 reference design in the ISE 9.1i Design Tools?

Solution

Add the following Area Group to the ML505 UCF file. The area group is required to meet timing on the PLB_DDR2 Core.  

 

AREA_GROUP "AG_DDR2" RANGE = SLICE_X0Y39:SLICE_X27Y0, SLICE_X0Y119:SLICE_X27Y80, SLICE_X12Y79:SLICE_X40Y40; 

INST "plb_ddr2_0" AREA_GROUP="AG_DDR2"; 

 

NOTE: For other ML505 board issues, please perform an Answer Record search for ML505.

AR# 24956
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article