We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24959

ChipScope Pro - ChipScope Pro IBERT for the Virtex-5 GTP cannot forward reference clock through 2 tiles


In ChipScope Pro IBERT v8.2 or 9.1 for the Virtex-5 GTP, there is a limitation on the ability to forward a reference clock from one tile, through another tile, to be used in a third tile.  


As an example, presume GTP X0Y0 has an input reference clock. The adjacent GTP, X0Y1, can be set through the Analyzer GUI to use this clock as its reference clock. This will work correctly. The issue arises if the next GTP, X0Y2, requires the use of this same clock. I can select GTP X0Y0 as the source, but the reference clock is not going to be correctly routed to this last GTP.


To work around this manually, set the reference clock multiplexer in the GTP by using the Analyzer GUI to interact with the GTP through the DRP interface.  


The attributes that must be set for any particular clocking scheme are discussed in Virtex-5 FPGA RocketIO GTP Transceiver User Guide: Appendix F "Advanced Clocking": 



The fix is scheduled for ChipScope Pro 9.2.01.

AR# 24959
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article