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AR# 24964

MIG v1.73 - Is further documentation available on the "Verify My UCF" option in MIG?

Description

Keywords: 1.7, Memory Interface Generator, Verify My UCF, guidelines

This Answer Record contains further information regarding the "Verify My UCF" option in MIG including:

General Information
Supported Verification
Unsupported Verification
Error Message Descriptions
- Uniqueness
- Association
- Clock-Capable I/Os for Strobes/Read Clock
- Absence of Signals
- Bank Selection

Solution

General Information
This feature allows the user to test whether a UCF file containing signal names and their corresponding pin names comply with the pin allocation rules for the selected options from the tool.
- All MIG input parameters for the generated design need to be selected for proper verification.
- Verification is performed only for the MIG-generated signals. Any additional signals in the user UCF are ignored.
- The input UCF must follow the MIG naming conventions. (Refer to the UCF generated by the MIG tool.)
Example for Virtex-4: DDR2 SDRAM controller 0 should have cntrl0_DDR2_DQ[0] for data bits, and RLDRAM controller 0 should have cntrl0_RLD2_DQ[0] for data bits.
Example for Virtex-5: DDR2 SDRAM controller 0 should have ddr2_dq[0] for data bits, and QDRII SRAM controller 0 should have qdr_d[0] for data write bits.

Supported Verification
- Virtex-4 and Virtex-5 designs only.

"Verify my UCF" verifies the following:
- All signals are allocated within the selected banks.
- Associated groups are allocated in the same bank. For example, DQ bits corresponding to a DQS are treated as a group in DDR/DDR2 memories. All the signals within the same group must be in the same bank.
- The selected data width. For example, if the current data width is set to 32 bits and the UCF has more bits, MIG verifies the required bits and then issues a warning message about the extra signals.
- The strobe/read clock signals are allocated to the Clock-Capable "P" pins when the CC pins option is enabled.
- MIG gives an error if two signals are allocated to the same pin or if the same signal is allocated to more than one pin.
- Note that verification is done for individual controllers separately in multi-controller cases.

Unsupported Verification
- Edit signal names option.
- Allocation of VREF and VRN/VRP pins.
- I/O standards and I/O voltages.
- WASSO limit.
- Reserved pins option.
- Frequency changes.

Error Message Descriptions
This section describes the different error messages that can be generated when verifying the UCF.

1. Uniqueness
If two signals are allocated to the same pins in the input UCF, an error message is listed in the user directed file. The error message format is "<signal_name1> and <signal_name2> are allocated to same pins."

For example, if cntrl0_DDR2_DQ[0] and cntrl0_DDR2_DQS[0] are allocated to the same pin, such as:
NET "cntrl0_DDR2_DQ[0]" LOC = "D12" ;
NET "cntrl0_DDR2_DQS[0]" LOC = "D12" ;
Then the following error message is printed:
ERROR: cntrl0_DDR2_DQ[0] and cntrl0_DDR2_DQS[0] are allocated to same pins.

2. Association
Signals in the same group (for example, assume DQS[0] and DQ[0:7] form a group) must be assigned to the same bank; otherwise, an error message is printed in the user directed file. The error message format is "<signal_name1> and <signal_name2> are not allocated in the same banks."

For example:
NET "cntrl0_DDR2_DQ[0]" LOC = "D12" ; #bank 6
NET "cntrl0_DDR2_DQ[1]" LOC = "C12" ; #bank 6
NET "cntrl0_DDR2_DQ[2]" LOC = "B10" ; #bank 6
NET "cntrl0_DDR2_DQ[3]" LOC = "C10" ; #bank 7

The following error messages are printed:
ERROR: cntrl0_DDR2_DQ[0](6) and cntrl0_DDR2_DQ[3](7) are not allocated in the same banks
ERROR: cntrl0_DDR2_DQ[1](6) and cntrl0_DDR2_DQ[3](7) are not allocated in the same banks
ERROR: cntrl0_DDR2_DQ[2](6) and cntrl0_DDR2_DQ[3](7) are not allocated in the same banks
These types of error messages are printed for all pairs of signals within the same group, even if only one signal is allocated to a different bank.

3. Clock-Capable IOs for Strobes/Read Clocks
If the option "Use Clock-Capable IOs for Strobes/Read Clocks" is enabled for Direct Clocking or SERDES is selected for the "Clocking Type," the strobe/read_clock signals should be allocated to CC pins. If this is not the case, an error message is displayed. The error message format is "<signal_name> should be allocated to the CC Pins."

For example, cntrl0_DDR2_DQS[0] is a strobe. Assume it is allocated to the K12 pin which is not a clock-capable IO pin. The following error message is printed:
ERROR: cntrl0_DDR2_DQS[0 should be allocated to the CC Pins.
ERROR: cntrl0_DDR_DQS[0] being Strobe should be allocated to the iotype of this pattern ^IO_L[0-9]+P_ (This pattern indicates 'P' pin of CC pair).

In the case of differential strobes, strobe should be allocated to the "P" pin of a CC pair and strobe# should be allocated to the "N" pin of the CC pair. If not, an error message is displayed. The error message format is "<signal_name> should be allocated to 'P'/'N' pin of CC pair."

For example, cntrl0_DDR2_DQS[0] is a differential strobe. Assume it is allocated to the C6 pin, which is not the "P" pin of a CC pair and cntrl0_DDR2_DQS_N[0] is allocated to B6 pin which is not the "N" pin of a CC pair. The following error messages are printed:
ERROR: cntrl0_DDR_DQS[0] should be allocated to 'P' pin of CC pair.
ERROR: cntrl0_DDR_DQS_N[0] should be allocated to 'N' pin of CC pair.
NOTE: The tool does not verify whether the differential pair is allocated to the same tile.

4. Absence of signals
If one or more signal-pin pairs is missing and/or commented in the input UCF, the verification result indicates the absence of those signal-pin pairs as a warning. The warning message format is "<signal_name> is not present in the given UCF against the selected inputs."

For example, assume the input UCF LOCs 8 bits DQ[0:7] but the selected data width in the GUI is 16 bits. When "Verify My UCF" is run, it verifies only eight bits and reports the other bits are not present as follows:

WARNING : cntrl0_DDR2_DQ[8] is not present in the given UCF File against the selected inputs.
WARNING : cntrl0_DDR2_DQ[9] is not present in the given UCF File against the selected inputs.
WARNING : cntrl0_DDR2_DQ[10] is not present in the given UCF File against the selected inputs.
WARNING : cntrl0_DDR2_DQ[11] is not present in the given UCF File against the selected inputs.
WARNING : cntrl0_DDR2_DQ[12] is not present in the given UCF File against the selected inputs.
WARNING : cntrl0_DDR2_DQ[13] is not present in the given UCF File against the selected inputs.
WARNING : cntrl0_DDR2_DQ[14] is not present in the given UCF File against the selected inputs.
WARNING : cntrl0_DDR2_DQ[15] is not present in the given UCF File against the selected inputs.

All the pins from the given ucf file have been allocated correctly. No. of pins missed in the selected ucf is 8.

5. Bank selection
If any pins are allocated in banks that are not selected in the MIG GUI, an error message is printed. The error message format is "<signal_name> (<signal_group>) is not supposed to be allocated in Bank (<bank_number>)."

For example:
NET "cntrl0_DDR2_DQS[0]" LOC = "D12" ;#bank 6
Bank 6 is not selected for Data (as cntrl0_DDR2_DQS[0] from Data). Assume that cntrl0_DDR2_DQS[0], which belongs to the strobe group is allocated to a pin belonging to bank 6. The following error message is printed:

ERROR: cntrl0_DDR2_DQS[0] (strobe) is not supposed to be allocated in bank 6.

Known Issues:
- In the case where DQS signal(s) is/are missing in the input UCF file, the following message will occur in the report file as many times as the number of missing DQS signals. This message occurs in addition to the message indicating that DQS is missing as indicated in the above "Absence of Signals" section.
ERROR: sig being 00 should be allocated to the iotype of this pattern ^IO_L[0-9]+P_ .

NOTE: This information is available in the MIG User Guide as of MIG v2.0 available with 9.2i IP Update #2.
AR# 24964
Date Created 09/04/2007
Last Updated 04/06/2009
Status Archive
Type General Article