UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24965

MIG v1.7 - ML461 board files output by MIG list incorrect setting for jumper location 'P10' when using the DDR2 SDRAM Direct Clocking design

Description

Keywords: ML461, board file, jumper, setting, P10, MIG, Memory Interface Generator, 1.7

The Chipscope project and Readme.txt files generated with the MIG v1.7 ML461 board files have the incorrect setting for jumper location "P10" for the Direct Clocking DDR2 SDRAM design . What is the correct setting for jumper location "P10"?

Solution

In all of the board files provided with the ML461, the Chipscope projects (.cpj file) use the default jumper settings of ML461 board. However, to properly verify the Virtex-4 Direct Clocking DDR2 SDRAM design board files provided with MIG v1.7, it is necessary to change the settings of jumper location "P10." The .cpj file provided for this design has the incorrect signal grouping and has the "P10" jumper setting as 1 and 2 connected. The correct setting, however, is 2 and 3 connected. The Readme.txt files output by MIG v1.7 also incorrectly list the setting as 1 and 2 connected. By setting the "P10" jumper to 2 and 3, the JTAG configuration chain bypasses the DDR memory. The .cpj files provided with the ddr2_v4 board files are tested by bypassing the ddr_v4 memory; hence, it is necessary to change the setting accordingly.

This will be resolved in the next MIG release.
AR# 24965
Date Created 09/04/2007
Last Updated 04/06/2009
Status Archive
Type General Article