LogiCORE RapidIO - Signal inversion needed when using ML523 rev D board or beyond

AR#	24967	Search For Another Answer
Topic	IP-RapidIO-Serial
Last Updated	10/15/2007
Status	Active

Description

Keywords: serial, high, speed, high-speed, PHY, logical, design environment, rio, rapid, IO, MGT, 9.1i, I/O, ml523, design, example, UCF, engineering, sample

When I generate a core with the Endpoint example (example design) targeting a Virtex-5 device, CORE Generator creates files that are needed to target the ML523 board.

Solution

In Serial RapidIO v4.2, there is a GUI selection to indicate an "Engineering Sample". When you select this option, it assumes that you are using ML523 Rev A, B, or C along with the Engineering Sample part, and the push buttons on the board (load, go, local_reset, link_reset) are not inverted. If you have ML523 Rev D and beyond, do not select "Engineering Sample". Not selecting "Engineering Sample assumes that you have production parts, and the design files generated will have inverted push buttons for ML523.

If you are still using Serial RapidIO v4.1, there is no selection for "Engineering Sample" and the example design files will be generated for ML523 Rev A, B, or C. If you have ML523 Rev D or newer, you must invert the signals from the push buttons in the Endpoint example design.

The signals in the "<component_name>/example_design/<component_name>_top.v" file that require polarity inversion are the following:

load
go
local_reset
link_reset

Edit the above file to invert the signals.