We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24993

MIG v1.7 - Stage 4 calibration of the Virtex-5 DDR SDRAM design does not find optimal calibration point or does not complete


Keywords: MIG, Memory Interface Generator, 1.7, calibration, DDR, optimal, complete

During Stage 4 calibration, the MIG v1.7 Virtex-5 DDR design does not find an optimal calibration point or does not complete.

NOTE: This calibration issue applies only to the MIG 1.7 Virtex-5 DDR (DDR1) Core. It does not apply to the Virtex-5 DDR2 Core.


"Stage 4" calibration (for DQS gate circuit) has a known issue where either:

1. The optimal calibration point to synchronize the DQS gate enable signal with respect to DQS is not determined. The circuit, however, can still work even without the optimal point.

2. The logic fails to finish calibration for Stage 4 and hangs. The particular result seen depends on various board delay factors (e.g., trace length, speed grade, etc.).

This will lead to marginal designs.

This was not seen in hardware testing on the ML561. The Stage 4 calibration was likely at a suboptimal point but does still work.

A work-around is currently under revision. The changes needed are in the "phy_calib.v/vhd" files. This Answer Record will be updated once the changes are finalized. If code is needed immediately, please open a case with Xilinx Technical Support at:

This issue is resolved in the MIG 1.72 release available with 9.1i IP Update #3. Please see (Xilinx Answer 24847) for further information on this IP Update.
AR# 24993
Date Created 09/04/2007
Last Updated 04/06/2009
Status Archive
Type General Article