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AR# 25018

Partial Reconfiguration - PlanAhead Flow FAQ / Know Issues for the Early Access Partial PlanAhead Program

Description

keywords:

This Answer Record is the Master Answer Record and will contain an FAQ, list of known issues, and links to other relevant ARs. Please reference this document for the latest information on the Partial PlanAhead program.

Solution

Known issues

The latest release is PR11 and has the following Known Issues.

ICAP and BSCAN range constraints are not obeyed by the placer code. Users may need to LOC these components to a given site and make sure the range constraint is consistent with the LOCs.

Gated global clocks may cause clock spine shorts if the play_opt algorithm is not turned off. If a global clock drives a data pin then the router will not obey the clock spine routing defined by the PR tools. The error message produced is as follows:

There were 1 overlaps (shorts) after routing.

The workaround is to set the environment variable to turn off the play_opt algorithm during static and/or PRM implementation.

This can be done by setting the following Environment Variable - RT_NO_PLAYOPT 1

FAQ

Q1: I am using the ICAP in my design, are there problems if I don't LOC that down to a site?

A1: The ISE tools will automatically select location X0Y0 for the ICAP (the bottom ICAP). This contradicts the top ICAP location expected by EDK tools. The user can use PlanAhead 9.2 to LOC the ICAP instance. Also, PlanAhead 9.2 has a DRC on ICAP instance. It will warn the user if the instance is not properly LOC'ed. If you do not LOC the ICAP it will be placed at this site. To LOC the ICAP in a PR design you need to apply a LOC constraint for an ICAP in the Static region. If you need to have your ICAP LOC'ed to a particular site in a PRR you need to apply a LOC and a RANGE constraint.

Q2: Can a non-rectangular area group be defined for my Partial Region? Such as an L-Shape?

A2: Yes, multiple Area group rectangles can be stitched together to create a non-rectangular Partial Reconfigurable Region. To do this, define an area group with multiple rectangular ranges. This can also be done in the PlanAhead by creating multiple PBlock rectangles for the Instance. The multiple rectangular ranges need to be contiguous.

** Using placement like this may reduce placement and routing efficiency and should be avoided where possible.

Q3: Can IOBs be included in a Partial Reconfigurable Region?

A3: Yes, IOBs can be included in a Partial Reconfigurable Region, and GUI support has been added to PlanAhead 9.2. To do this in the UCF file assign the INST to the Area Group. This can also be done in the PlanAhead GUI by enabling the IOB grid of the pblock, and then assigning the connected buffers of the IOBs to a PBlock. See page 16 of 26 in the "Partial Reconfiguration Design with PlanAhead" User Guide. IOBs should either be instantiated in the PRR or have the signal tagged with the buffer_type attribute which is picked up by XST. A RANGE constraint should also be added that includes all IOBs in the PRR. For more information please refer to the Partial Reconfiguration User Guide, UG208, Chapter 2: The Early-Access Partial Reconfiguration Design Flow; Section HDL Design Rules for PR Modules

Q4: What are the differences between single slice and Narrow/Wide bus macros which use multiple slices?

A4: Single Slice bus macros are only available with V-5. These are direction independent and the macros need to be placed within the partial reconfigurable module. Single slice Macros are contained within one slice and do not straddle the PR boundary.

The Narrow/Wide bus macros are available with V-4, Virtex-II Pro and Virtex-II. These macros are direction dependent and allow for signals to move from right to left or left to right in and out of a region.Designs being migrated to Virtex-5 will need to have the new bus macros included in the design, and the Single Slice macros will have to be re-instantiated and re-placed. For more information please refer to the Partial Reconfiguration User Guide, UG208, Chapter 3: Bus Macros.

Q5: How do I handle budgeting for timing information?

A5: In the PR design it is recommended that signals are registered at the module boundary. Timing constraints can be created for the path going to/from the register at the module boundary. The merged NCD file will be used for timing analysis and simulation. However, a merged PCF is not created so timing analysis is limited.

Q6: What components can not be included in a PRR?

A6: Global Buffers (BUFG) and DCM's can not be included in a partial reconfigurable module. This is due to a limitation with fabric which will not allow the clock frame to include partial reconfigurable sections. For inclusion of BUFR primitives please refer to the White paper on inclusion of a BUFR in a PRR: http://www.xilinx.com/support/prealounge/protected/docs/wp344_draft.pdf

Q7: Why is the update netlist button Greyed out in PlanaAhead for PR projects? Can I work around this?

A7: This was greyed out due to additional complexity in the PR Project netlist data structure. It will be fixed in a future release of PlanAhead. The is to close PlanAhead and manually copy the updated netlist into the design.data\netlist directory, then relaunch PlanAhead. This will be enabled for the Static netlist in PlanAhead 10.1.05.

Q8: Can I apply a TPSYNC Timing Constraints to an asynchronous path crossing a Bus Macro?

A8: TPSYNC constraints are currently not supported.

Q.9 Can I Insert ChipScope in my PRM?

A.9 ChipScope can be inserted in a PRM but this is not yet documented. If you need ChipScope support contact your FAE and open a WebCase:

http://www.xilinx.com/support/clearexpress/websupport.htm

Q.10 Is Virtex-5 Supported for PR designs?

A.10 Virtex-5 is available in the tools for PR designs but is not a fully supported device. There are software issues that can not be resolved in ISE 9.2i that the EA PR tools are build on.

Q.11 How do I use the ICAP for loading partial bit files?

A.11 Documentation on the ICAP can be found in the Virtex-4 Configuration User Guide or the Virtex-5 Configuration User Guide:

http://www.xilinx.com/support/documentation/virtex-4.htm
http://www.xilinx.com/support/documentation/virtex-5.htm

Additional information can be found in the Partial Reconfiguration User Guide, UG208,Chapter 5: Combing the Early Access PR and EDK Design Flows. There are also EDK peripherals available that can be used to drive the ICAP. The OPB_HWICAP and XPS_HWICAP.

Q.12 What Operating Systems are the EA PR tools Supported on?

A.12 The EA PR tools are supported on 32-bit Windows XP and Red Hat Linux 4 (32 bit).

Q.13 How do I work around the "ERROR: There were 1 overlaps (shorts) after routing." in Final Assembley?

A.13 The short term work around to the "There were 1 overlaps (shorts) after routing" problem is to set the environment variable setenv RT_NO_PLAYOPT 1.

There are two environment variables to set in order to make the PR merge process report clock spine assignment and the shorted nets more clearly.

setenv XIL_PR_MERGEVERBOSE 1

setenv XIL_PR_SPINEDEBUG 1

If you run into this problem please re-run implementation with these environment variables set contact your FAE and open a WebCase:

http://www.xilinx.com/support/clearexpress/websupport.htm

Q.14 When I run PR_Verifydesign I see "ERROR: Net <Bus Macro Net Name> crosses boundary illegally.". When I open up the NCD in FPGA editor the placement of the Bus Maco seems correct. What is the problem?

A.14 This problem can occur when a horizontal Trusted Bus Macro straddles a BRAM column. The BRAM interconnect in the switch matrix is not available for hard macros like a Bus Macro. PlanAhead does not have a DRC for this so this may be the issue here.

If this is not the case and the placement of the Bus Macro crosses a legal PRR to Static boundary then contact your FAE and open a WebCase:

http://www.xilinx.com/support/clearexpress/websupport.htm

Q.15 I encounter the following PAR error when I use an L shaped Area Group:

Phase 2.7

ERROR:Place:835 - Given the original pre-placement, no legal placements can be found for XXXX group(s). The following is

the description of these group(s). The relative offsets of the components are shown in brackets next to the component...

A.15 This is a known issue. Contact your FAE and open a WebCase:

http://www.xilinx.com/support/clearexpress/websupport.htm

Q.16 Will I see identical Implementation results for a Design in the Production ISE as I do with the Patched PR ISE tool flow?

A.16 If you use the same implementation options used and your deisgn is tightly constrained you can expect similar but not identical results. Depending on the design utilisation and how well constrainted the design is there will be differences in Implementation. The patched PR tools include modifications to the Map and PAR algorithm which can effect implementation and may result in less optimal timing.

Q.17 The UCF parser in PAR does not recognize multi-line constraints for slice ranges.

A.17. The only syntax that works is as follows:

AREA_GROUP "area_group_name" RANGE=SLICE_X??Y??:SLICE_X??Y??,SLICE_X??Y??:SLICE_X????, SLICE_X??Y??:SLICE_X??Y??;

Q.18 What constraints should I use for non-rectangular PRRs?

A.18 Non-rectangular PRRs can be created with contiguous ranges for area groups. An additional constraint is required in these circumstance -

AREA_GROUP "area_group_name" PLACE=EXPAND/NO;

The above constraint should be added to the Areas Groups.

Q.19 Can I use wildcards in my UCF constraints with a PR design?

A.19 No you cannot use wildcards in a UCF with the EA PR flow.

Q.20 I duplicated the one of the Floorplans in my PR design using PlanAhead. In this newly created Floorplan I removed a PRR by using the ?Unset Reconfigurable? option, and now I receive Internal Exceptions when I try to open the Floorplan. How can I get around this error?

A.20 This issue can be worked around by creating a new project.

AR# 25018
Date Created 10/28/2007
Last Updated 03/22/2010
Status Archive
Type General Article