LogiCORE XAUI - Virtex-4 VHDL example design has an undriven signal which causes Synplify to trim GT11 init blocks
Description
Keywords: 10, Ten, Gigabit, Ethernet, MAC, known, issues, release, notes, patch, installation, instruction, v7.1, v7.0, ip2_im, IP Update 2, Virtex-5
In XAUI v7.1 (and earlier) for Virtex-4, when the core is generated with no MDIO interface in <core_inst_name>_block.vhd, the signal soft_reset is not driven and not initialized.
From <core_inst_name>_block.vhd:
signal soft_reset : std_logic;
...
mgt_reset_terms <= reset or soft_reset;
Synplify 8.6.1 infers an initial value of "1" for this signal, which causes the rx and tx init blocks to be removed from the design, and this causes the design not to work.
Solution
To work around this issue, change the code so that is does not use soft_reset:mgt_reset_terms <= reset;
This is only an issue for the VHDL Virtex-4 example design without the MDIO interface. This signal is also not driven in Verilog, although the trimming of the init blocks is not seen in the Verilog Synplify synthesis (since soft_reset is initialized to "0"). This is not an issue in XST, because it initializes soft_reset to "0" in both VHDL and Verilog.