We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25027

9.1i XST - Why does XST insert BUFGs on my set and reset signals when I target a Virtex-5 device?


Why does XST insert BUFGs on my setand reset signals when I target a Virtex-5 device?


XST inserts BUFGs for control signals with a fanout of over 3000.
The BUFGs use special routing resources for high fanout control signals which in turn reduce the regular routing resources, this makes the design easier to route.
If you would like to control the BUFG insertion, you can use the buffer_type attribute to prevent or add BUFG insertion on specific signals.
For information on buffer types, refer to page 334 of the XST User Guide:
AR# 25027
Date Created 02/07/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less