UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25032

LogiCORE Endpoint Block Plus v1.5 Rev 1 EA for PCI Express - What are the known issues when targeting Virtex-5 ES silicon with the LogiCORE Endpoint Block Plus?

Description

This Answer Record lists the known issues associated with targeting the LogiCORE Endpoint Block Plus for PCIe on Virtex-5 engineering sample silicon (ES).

Solution

Xilinx strongly recommends that you target production Virtex-5 devices and the LogiCORE Endpoint Block PLUS for PCIe when targeting the Integrated PCI Express block. There are known issues in the Virtex-5 ES silicon as listed in the errata (http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1212267)that might impede performance and functionality when using the Block Plus core for PCI Express as discussed in this Answer Record.

ES silicon are not warranted for production release usage and Xilinx LogiCORE solutions used in ES silicon are not warranted for production release usage. The following are the known issues when targeting the LogiCORE Endpoint Block PLUS for PCIe on Virtex-5 ES silicon.

See (Xilinx Answer 24697) to obtain the EA patch for the Block Plus Core needed to target Virtex-5 ES silicon.

Transaction Ordering

Issue: On the receive interface, completion packets can be blocked by non-posted packets.

Impact: The design and system might appear to hang. A user application waiting for a completion packet must drain the non-posted queue to ensure that the completion packet already in the Rx buffer can be drained. Users of the Block Plus Core should keep trn_rnp_ok_n asserted at all times, but the problem might still occur under some conditions. A reset must be issued to correct the problem.

Issue: On the transmit interface, completion packets can be blocked by non-posted packets.

Impact: The design and system might appear to hang. You can work around this by freeing up non-posted flow control credits in the link partner device. However, in most systems you will not have this type of control over link partner devices. In most cases, the link partner will automatically free non-posted flow control credits over time.

Issue: When running as an 8-lane application, posted packets might be transmitted even if the link partner is advertising no credits are available. This can occur when the link partner does not advertise infinite completion flow control credits.

Impact: This might result in a system crash. Users of the Block Plus Core cannot work around this problem because link partner credit information is not provided to the user application. A reset must be issued to correct the problem.

Issue: Posted packets accepted by the Block Plus Core can be bypassed by following completion of non-posted packets.

Impact: The design and system might appear to hang. Users of the Block Plus Core cannot work around this problem because link partner credit information is not provided to the user. A reset must be issued to correct the problem.

Configuration Space

Issue: The Data Link Layer Link Active Reporting Capable bit [20] of the Link Capabilities register is incorrectly set to "1." The Data Link Layer Link Active bit [13] of the Link Status Register is incorrectly set to a "1."

Impact: The functionality of the core is not affected. However, when running the PCIECV test, the TD_1_5 test fails because of this problem.

Issue: The Version field of the Power Management capability is incorrectly set to "010b."

Impact: The functionality of the core is not affected. However, when running the PCIECV test, the TD_1_16 test fails as a result of this problem.

Reset Mode

Issue:The Block Plus Early Access patch uses the 4-pin Reset Mode to reset the integrated block for PCI Express.

Impact: The 4-pin reset mode may not work reliably in all circumstances during hot reset sequences, possibly resulting in a system hang. If this happens, the system must be power cycled.

AR# 25032
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article