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AR# 25035

LogiCORE Fibre Channel and Fibre Channel Arbitrated Loop - To avoid BER failures it is important to ensure board meets Virtex-2 Pro MGT specifications


For Virtex-II Pro board designs, it is important to consult and meet the Power, REFCLK, SSO, and Signal Integrity specifications in the Virtex-II Pro User Guide (UG012) and RocketIO Transceiver User Guide (UG024): 



It is especially important to meet these specifications when operating at lower line rates such as the 1G Fibre Channel line rate. BER failures can occur in boards with bad reference clocks, noisy power supplies, and outside the SSO and Signal Integrity specifications.

AR# 25035
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article