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AR# 25040

MIG v1.7 - MIG does not provide a DDR DIMM or DDR2 SODIMM design for Virtex-5. Can a DDR/DDR2 component design be modified to interface to a DDR DIMM/DDR2 SODIMM?


The current release of MIG, MIG 1.7, does not provide a DDR DIMM design or a DDR2 SODIMM design for Virtex-5. Only DDR component designs and DDR2 component and registered DIMM designs are available. How can I modify the DDR/DDR2 component designs to interface to a DDR DIMM/DDR2 SODIMM?


Use the following steps to modify a MIG DDR component design to interface to a DDR DIMM, or a MIG DDR2 component design to interface to a DDR2 SODIMM. These steps are provided as a starting point; full simulation and hardware verification are required.

1. From MIG, select the component used within the target DIMM.

If the component used in the DIMM is not available, you can use the "Create New Memory Part" feature to input the component parameters. Then, increase the "Data Width" to match the DIMM width.

As an example, the MT8VDDT6464A DIMM module uses MT46V64M8TP DDR SDRAM devices. In MIG, you would select the MT46V64M8XX-5B device and change the width to 64 bits. This generates a 64-bit component DDR design with eight 8-bit components.

2. It is recommended to use the MIG-generated pin-out as a starting point.

Ensure the following guidelines in addition to those outlined in Appendix A of the MIG User Guide are followed when selecting banks from the MIG GUI:

- DQS must be placed on clock-capable I/O pins - must be routed to the "P" side of the C/C I/O pair.

- DQ bits must be placed on the same bank as the corresponding DQS. Preferably, the DQ bits belonging to the same bank should be placed on consecutive I/O tiles on the same I/O column. Use the FPGA Editor to view; this will reduce clock skew between DQ bits.

- DM (data mask) pins can be placed next to the corresponding DQ pins or in the "N" side of the C/C I/O pair. MIG chooses the "N"-side of the C/C IO pair; however, you can modify this output UCF to place the DM pin(s) near the corresponding DQ pins.

- Control, address, CLK/CLK_N outputs should be placed in the same bank. CLK/CLK_N is a differential input, so should be placed on a single differential pair.

- Data and Address and Control should be located in consecutive vertical banks.

- The MIG 1.7 design employs a scheme to gate the incoming DQS strobe (to prevent glitches seen at the end of a read burst). This scheme requires three pin-specific LOC constraints per DQS (e.g. 12 constraints for a 32-bit, 4-DQS design) to locate two IDELAY components and one SLICE flip-flop. The UCF file describes these constraints. If DQS is moved, ensure these constraints are moved in relation to DQS.

3. Modify the MIG generated UCF to:

- Adjust I/O standard of outputs (i.e., switching from SSTL2_I to SSTL2_II if more drive is required).

- Account for differences in the user-desired pin-out from the MIG-generated pin-out. Only remove those I/O that do not exist on the DIMM (e.g., unused clock outputs, DIMM reset).

4. As needed, change the widths of the output signals.

- Some signal widths might need to be changed due to differences in pin-out between the multi-component and DIMM design. For example, if MIG generates 4 x16 devices, MIG provides four clock (CLK) pairs; however, the DIMM only needs three. The number of CKE pins also changes. Refer to the DIMM data sheet for appropriate signal widths.

- It might be necessary to replicate and output multiple copies of signals (e.g., control/address) to improve signal integrity. Make sure to run an IBIS simulation for verification.

5. Modify for registered DIMMs.

- The top-level REG_ENABLE parameter in the HDL should be set to one. This accounts for the extra clock cycle delay in the control/address reaching the memory devices on a registered DIMM.

- Add an additional active-low reset output, ddr_reset_n. This output is the reset to the address/control register on the DIMM module. The MIG design needs to assert this reset whenever the MIG core is held in reset. To add this to the component MIG design, declare the output port in the top-level (mem_interface_top.v/vhd) port declaration, and then assign the output the negation of rst0 (Verilog version shown below):

assign ddr_reset_n= ~rst0;

NOTE: These steps are applicable to both single- and dual-rank DIMM interfaces. However, in addition to these steps Dual-Rank DIMM interfaces also require separate calibration of each rank, and so additional logic is required. Xilinx has not implemented this configuration and, consequently, cannot guarantee the maximum frequency specified for Virtex-5 DDR SDRAM component operation.

MIG v2.0 includes support for Virtex-5 DDR DIMM and Virtex-5 DDR2 SODIMM designs.
AR# 25040
Date Created 09/04/2007
Last Updated 11/09/2011
Status Archive
Type General Article