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AR# 2505

Mixed Voltage Systems - Interfacing 3.3 Volt and 5 Volt devices


Keywords: Mixed, Voltage, 3.3V, 5V, I/O, config

As low voltage (3.3v) CMOS devices become more and more prevalent, connections between older (5V) devices becomes a growing concern. This Answer Record briefly describes the concepts of connecting and configuring these mixed-voltage devices with Xilinx FPGAs.



Connecting 5V devices to Xilinx 3.3V FPGAs.


5V Outputs Driving XC4000XL Inputs
The XC4000XL I/O structures have been designed to tolerate a
constant input voltage of 5.5V using only the single 3.3V power
supply connected to the device. In fact, they are 5V tolerent
even without being powered up. This means that any 3.3 or 5
Volt (CMOS, TTL, Pullup, or Vcc) may be safely attached to an
XC4000XL input without the use of any current limiting
resistors or worries about power-up sequencing.

XC4000XL Driving 5V Inputs with TTL Thresholds
The XC4000XL can directly drive any 5V device with TTL
Threshold levels. The XC4000XL outputs drive rail to rail and
thus completely meet all TTL Standard Specifications.

XC4000XL Driving 5V Inputs with CMOS Thresholds
According to the standard specifications for CMOS thresholds,
the VIHmin (Voltage Input logic High minimum voltage) is 70%
VCC (where VCC is that of the target device) which is 70% of 5
volts = 3.5 volts. The outputs of the XC4000XL drive to rail
which is 3.3 volts. So, by virtue of worst case numbers we
miss the spec by 0.2 volts under these conditions.
Fortunately, we have options:

Can the 0.2 Volts safely be ignored?

1. Yes. Typical devices do not operate on the minimum
specifications. For example, on the xc4000XL device there is
no actual VIH and VIL. There is one actual threshold level at
1.8 volts with a hysteresis of 100mV. All specifications are
very conservative across the industry. It's not likely that a
5 Volt CMOS device would interpret 3.3 Volts on an input as a
logic LOW.

If this 0.2 volt discrepancy cannot be forgiven, please choose
from the following...

2. Increase the XC4000XL supply voltage to 3.6 volts. That
will bring the outputs voltage above the specified minimum.

3. The Open-Drain Output Solution. Configure the outputs of
the XC4000XL design to use OBUFTs such that they will drive LOW
and tristate for logic LOW and HIGH, respectively. Connect
individual pullup resistors from the open-drain outputs to the
target supply voltage (5Volts). The smaller the resistor used,
the faster transition will be obtained.

Note: See also solution record 2760.

XC3000L and XC3100L

5 Volt Outputs Driving XC3000L and XC3100L Inputs
The XC3000L and XC3100L protection circuitry is designed in the
more traditional manner which can not sustain voltages above
VCC (3.3V) for any length of time. Because of this, a 150 Ohm
current-limiting resistor is recommended to guarentee the input
current of less than 10mA which is generally considered safe
level flowing through the ESD diodes.

XC3000L and XC3100L Driving 5V Inputs
The specified VOH minimum of the XC3000L and XC3100L families
is 2.4 volts which is greater than the specified minimum 2.0V
for TTL Threshold levels, thus these device families may be
interfaced with with any 5V TTL level input. If the XC3000L
and XC3100L families are needed to drive 5V CMOS levels or
levels close to 5V, external circuitry will need to be added to
drive this threshold.


NOTE: This solution contains more than one resolution.

When connecting a 5 Volt FPGA to a 3 Volt device, the FPGA should be configured to use TTL level thresholds. CPLDs can have their VCCIO connected to the interface voltage (3.3V).

XC4000, XC4000H, XC4000E, XC4000EX

Driving 3.3V Inputs
The XC4000 FPGAs have n-channel "totem-pole" output structures that drive little current at VOH. Due to this fact, the XC4000 device can directly drive a 3.3V input safely (without a current-limiting resistor) provided the 5 Volt supply voltage does not exceed 5.25 Volts and the device outputs are configured for TTL threshold levels.

Receiving 3.3V Outputs
3.3V CMOS devices may directly drive any XC4000 device. The minimum input logic high threshold VIHmin for the XC4000 family with TTL level inputs is 2.0V which is less than the minimum VOH (CMOS) threshold specification for 3.3V devices.

XC2000, XC3000/A, XC3100/A, and XC5200

Driving 3.3V Inputs
These device families have complimentary output structures. It is suggested to connect current-limiting resistors to the I/O for all non-5 volt tolerant 3.3V devices in order to protect the 3.3V device inputs and ESD protection circuitry. The size of the current limiting resistor should be no less than 150 Ohms. This should guarantee an input current below 10mA. This is generally considered safe for most CMOS 3.3 volt devices, but please review the device specifications or contact the manufacturer to ensure this to be true.

In general, care must be taken to avoid forcing the 3.3V supply voltage above its 3.6V maximum whenever a large number of
active hign inputs drive the 3.3V device. Potentionally, this could cause the 3.3V supply current to reverse direction. Also, the 3.3V Vcc power should be on before driving the device inputs from a 5V device.

Receiving 3.3V Outputs
3.3V CMOS devices may directly drive any XC2000, XC3000, or XC5200 FPGA as long as the FPGA is configured for TTL input
levels. The minimum input logic high voltage (VIH) for these devices is 2.0 Volts which is less than the TTL Threshold Standard VOH which is 2.4 Volts.

XC7300 and XC9500

Driving 3.3V and 5V Inputs
For Xilinx CPLDs, the I/O ring can be powered by either a 5V VCCIO or 3.3V VCCIO. When the I/O is powered by a 3.3V Vccio,
the CPLD may safely drive any 3.3V or 5V (with TTL levels) device. If the device is connected to a single supply (VCCIO = 5V), a current limiting resistor is suggested to be connected between the output of the CPLD and input of the non-5V tolerant 3.3V device, no less 150 Ohms.

Receiving 3.3 and 5V Outputs
Regardless of the supply voltage on the VCCIO pin, the XC7300 and XC9500 can accept 3.3V and 5V (CMOS or TTL) level inputs.


Configuration issues with mixed 3.3V and 5V devices

Configuring a 5V FPGA with a 3.3V PROM

Since the configuration pins of the 5V FPGAs are all TTL level inputs and outputs, a 3.3V PROM may be directly connected to an XC4000 family FPGA without any external circuitry. For the XC3000 and XC5200 families, unless the PROM has 5V tolerant I/O, a current limiting resistor of no less that 150 Ohms is suggested on all outputs of the XC3000 or XC5200 that connect directly to the 3.3V PROM.

Daisy Chaining Mixed Voltage Devices
All Xilinx FPGA Configuration pins are TTL compatible. Daisy chain configuration can be performed with mixed-voltage FPGAs without additional circuitry.

The only exception to this is when the XC3000L and XC3100L families are the lead device in a daisy chain with 3.3V or 5V XC4000 and/or XC5200 families following. In this case, two options should be considered.

1. Place the XC3000L and/or XC3100L in the back of the daisy chain and separate the 5V devices from the 3.3V devices with current-limiting resistors on all interfacing configuration pins.

2. Use the XC3000L or XC3100L as the lead device and use the circuit discussed on page 4-55 of the 1996 databook to add the additional needed CCLKs for the XC4000 and XC5200 devices in the daisy chain.

Using the XCHECKER with 3.3V FPGAs
The XCHECKER cable can be used to download to 3.3V FPGAs and mixed voltage daisy chains. Since the XCHECKER cable contains a 5V FPGA, the cable either needs to be supplied a 5V source with a common ground to the download board or the 3.3V adapter needs to be used to allow the cable to operate with a 3.3V power source.

When downloading to an XC4000XL or XC5200XL, the XCHECKER can be directly connected to the FPGA in the normal fashion
regardless whether it is powered by a 5V source or the 3.3V adapter. If the cable is to be connected to an XC3000L or XC3100L, it is suggested to use the 3.3V adapter and the XCHECKER cable may be directly connected to the device. If the
3.3V adapter is not availible, the XCHECKER may be powered with a 5V source and use current limiting resistor on all cable connections to the FPGA of no less than 150 Ohms.

NOTE: For information on obtaining a 3.3V adapter for the XCHECKER cable, please contact your local Xilinx Distributor or Sales representative.
AR# 2505
Date Created 08/31/2007
Last Updated 11/05/2008
Status Archive
Type General Article