Keywords: IDELAYCTRL, replication, constraints, optimization
The Virtex-5 User Guide (UG190) has the following description of how the implementation tools handle IDELAYCTRL components. It mentions that IDELAYCTRLs are replicated if they are not constrained. What are the rules for this replication?
(See "IDELAYCTRL Usage and Design Guidelines", under the IDELAYCTRL Overview):
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides"Instantiating IDELAYCTRL Without LOC Constraints
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code. The implementation tools autoreplicate
IDELAYCTRL instances throughout the entire device, even in clock regions not
using the delay element. This results in higher power consumption due to higher resource
utilization, the use of one global clock resource in every clock region, and a greater use of
routing resources. The signals connected to the RST and REFCLK input ports of the
instantiated IDELAYCTRL instance are connected to the corresponding input ports of the
replicated IDELAYCTRL instances."