I receive the following warning by the timing tools for my Virtex-5 DCM when using the CLKIN_DIVIDE_BY_2 DCM attribute:
"WARNING:Timing:3326 - Timing Constraint "TS_SRC_CLK = PERIOD TIMEGRP "SRC_CLK" 400 MHz HIGH 50% INPUT_JITTER 0.05 ns;" fails the maximum period check for output clock src_u0/b14_v8_3_pl4_src_top0/U0/clk0/SrcClk_dcmo from DCM_ADV src_u0/b14_v8_3_pl4_src_top0/U0/clk0/tdd because the period constraint value (5000 ps) exceeds the maximum internal period limit of 4167 ps. Please reduce the period of the constraint to remove this timing failure."
Why do the tools report a maximum period internal limit of 4167 ps (equaling a minimum frequency of 240 MHz) when the Virtex-5 Data Sheet specifications indicate that the minimum frequency for the CLK0 output is 120 MHz?
This warning should be ignored. The timing tools are incorrectly referring to a 240 MHz minimum frequency for the CLK0 output when the CLKIN_DIVIDE_BY_2 DCM attribute is set to True. The CLKIN_DIVIDE_BY_2 attribute should not have an impact on this output, and the minimum frequency should be 120 MHz.
This problem has been fixed in the latest 9.2i Service Pack available at:
The first service pack containing the fix is 9.2i Service Pack 2.