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AR# 25063

CPLD CoolRunner II - How can you analyze the timing of a transparent latch?

Description

How do you analyze the timing of a transparent latch?

Solution

The constraints below can be used. In the example, GATE should be replaced by the signal you have connected to the gate input to the latch. 

 

NET "GATE" TNM_NET = "GATE"; 

OFFSET = OUT 10 ns AFTER " GATE "; 

NET "GATE " BUFG=CLK; 

 

In ISE 9.1i, the latch cannot be analyzed as it is implemented differently (the functionality is correct). 

 

This will be resolved in ISE 9.2i and also worked in ISE 8.2i.

AR# 25063
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article