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AR# 25067

Virtex-4/-II Pro Aurora v2.7 - Release Notes and Known Issues for 9.1i IP Update 3 (9.1i_IP3)

Description

This Release Notes and Known Issues Answer Record is for the Virtex-4 and Virtex-II Pro Aurora v2.7, released in 9.1 IP3, and contains the following information: 

- New Features 

- Known Issues  

 

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).

Solution

Release Notes 

 

- Generation of Aurora Core is now possible by invoking COREGen from ISE  

 

Bugs Fixed in v2.7 

 

- CR 436773: Incorrect values assigned for VCODAC_INIT and CPSEL 

- CR 436564: COREGen GUI displays invalid frequency values for GT11 reference clocks 

- CR 436364: Simplex partner simulation fails due to errors .do file 

- CR 434801: Missing descriptions for input ports, RX_SIGNAL_DETECT and RESET_CALBLOCKS in LogiCORE Aurora v2.7 User Guide (UG061.pdf) 

- CR 433684: Aurora incorrectly sets ENABLE_DCDR to TRUE for 1.5Gbs 

- CR 433301: License status dialog incorrectly indicates you do not have access to source code for the Aurora Core 

- CR 432196: Incorrect description for SYNC_CLK LogiCORE Aurora v2.7 User Guide (UG061.pdf)  

 

Known Issues 

 

- Important! Please see (Xilinx Answer 25470) 

- There is a bug in the Xilinx NGDBuild and MAP tools that prevents Virtex-II ProX modules using REFCLK from being processed correctly. To work around this issue, the BREFCLKNIN and BREFCLKPIN signals from all the MGTs must be connected to pins at the top level of the module. REFCLK will still be used as the reference clock for the MGT.

AR# 25067
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article