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AR# 25080

9.1i sp3 Timing Analyzer - "WARNING:Timing:3238 - Timing Constraint <...> fails the minimum period check..."

Description

I am using a Virtex-4 FX device (speed grade:-11), and no APU is used. When implementing the design, I receive the following warnings:

"WARNING:Timing:3238 - Timing Constraint

"TS_ppc_sub_system_pmcd_0_pmcd_0_CLKC1_BUF = PERIOD TIMEGRP

"ppc_sub_system_pmcd_0_pmcd_0_CLKC1_BUF" TS_ppc_sub_system_clk_400MHz HIGH 50% INPUT_JITTER 0.15 ns;"

fails the pulse width check for clock ppc_sub_system/clk_400MHz_pmcd because the low value (1250 ps) or high value (1250 ps) is less than the minimum internal pulse width limits of 1666 ps low and 1666 ps high. Please increase the period of the constraint to remove this timing failure. "

"WARNING:Timing:3232 - Timing Constraint

"TS_ppc_sub_system_pmcd_0_pmcd_0_CLKC1_BUF = PERIOD TIMEGRP

"ppc_sub_system_pmcd_0_pmcd_0_CLKC1_BUF" TS_ppc_sub_system_clk_400MHz HIGH 50% INPUT_JITTER 0.15 ns;"

fails the minimum period check for clock ppc_sub_system/clk_400MHz_pmcd because the period constraint value (2500 ps) is less than the minimum internal period limit of 3332 ps."

What do these warning messages mean?

Solution

The Speed file and tool support PPC405 400 MHz and timing will issue a warning ONLY when stepping level is set to ES or SCD1.

There is no warning for stepping level 0 or 1 for the Production devices.

The Virtex-4 Data Sheet indicates that the maximum input frequency the PPC405 can achieve is 400 MHz at the -11 speed grade.

AR# 25080
Date Created 09/04/2007
Last Updated 01/18/2010
Status Archive
Type General Article