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AR# 25082

LogiCORE Endpoint for PCI Express - Is there an 8-lane (x8) downstream port simulation model available?


Is there an 8-lane (x8) downstream port simulation model available?

How can I test the completion streaming mode when using the LogiCORE Endpoint Block Plus for PCI Express?


Currently, Xilinx provides a downstream port simulation model that operates as either x4 or x1. It does not operate as a x8. Currently, there are no plans to provide a x8 downstream port simulation model. For PCI Express, Xilinx provides a working x4 and x1 model that allows you to functionally simulate your design. However, this is not a full Bus Functional Model (BFM). Regardless of whether you are running in x8 vs. x4 or x1, the user logic operates the same. Consequently, the model provided allows you to simulate your design and check functionality.

If you need more advanced features when testing your user application, you can investigate obtaining a BFM from another vendor. Note that Xilinx has thoroughly simulated and verified that the core itself is protocol compliant to the PCI Express Base Specification. This was accomplished using our own internal bus functional model that runs an extensive set of tests to check the core.

In most cases, the provided simulation model along with the example test bench is sufficient to verify most user application designs. The only time where this might be an issue is when using the Virtex-5 Block Plus Core in x8 mode with a 250 MHz user application implementing completion streaming. Completion streaming is an optional mode that allows for increased performance when receiving completions to outstanding memory reads. If the core trains down to x4 and the user interface is still running at 250 MHz, then completion streaming is not needed. Consequently, the simulation does not truly represent the functionality.

In this case, the options are as follows:

- A possible way to work around this issue, is to run the x4 core, but change the user interface clock to 125 MHz. This gives you the same coverage from the user application perspective as the x8 running at 250 MHz. However, the provided model is not designed to issue back-to-back completion packets on the link at the rate at which you might be trying to test. In other words, the downstream port model provided is not meant to be a full BFM so it was not designed to pump completions out on the link at such a high rate. It is important to be aware of this limitation.

- Create a dummy model to test the completion streaming logic. To do this, create an interface that mimics the Block Plus Core solely to test this part of the logic. The idea is to send a stream of completion packets into the logic in a constant stream similar to what you expect off the link. The worst case is to set it up so it sends a completion packet one after the other with no cycle between the first packet EOF and next packet SOF.

- The other option is to purchase a third-party BFM that is capable of issuing back-to-back completions similar to what might occur in a real system.

Revision History

02/20/2008 - Initial Release

AR# 25082
Date Created 02/20/2008
Last Updated 12/15/2012
Status Active
Type General Article