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AR# 25088

LogiCORE RapidIO v4.1 - RX and TX PLLs might fail to lock or exhibit excess jitter due to incorrect MGT settings

Description

For Virtex-4 devices, the recommended settings for the VCODAC_INIT, RXVCODAC_INIT, TXCPSEL, and RXCPSEL attributes have changed since the srio_v4_1 release. If not updated, the RX and TX PLLs might fail to lock or exhibit excess jitter.

Solution

This issue is fixed in v4.2 of the Serial RapidIO core. 

 

For a v4.1 work-around: 

The current recommended settings for the VCODAC_INIT, RXVCODAC_INIT, TXCPSEL, and RXCPSEL attributes for each line rate are described in the following table: 

 

GT11 Attribute ............ 3.125 Gbps .....2.5 Gbps ......1.25 Gbps  

VCODAC_INIT ................ 0x029 ........... 0x005 .......... 0x005  

RXVCODAC_INIT ........... 0x029 ........... 0x005 .......... 0x005  

TXCPSEL ........................ TRUE............ FALSE ........ FALSE  

RXCPSEL .........................TRUE ........... FALSE ........ FALSE  

 

Please update the attribute settings for each GT11 used in the srio_v4_1 Core. By default, these attributes are located in the "rocketio_wrapper_v4_1x.v" and "rocketio_wrapper_v4_x4.v" files. If this is a x4 design, be sure to update the attributes for all four MGTs. 

 

For more information on this issue, refer to (Xilinx Answer 24656).

AR# 25088
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article