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AR# 25096

Spartan-3A DSP FPGA-DSP48 - Why does the Spartan-3A HDL Libraries Guide not have an instantiation template for the DSP48A in the ISE 9.1.03i release?

Description

Keywords: Xtreme DSP, slice, DSP48, DSP48A, Spartan-3A DSP, Spartan-3A, template, libraries guide

Why does the Spartan-3A HDL Libraries Guide not have an instantiation template for the DSP48A?

The DSP48A template is marked as "To Be Determined" for ISE 9.1.03i. For this release, you can use the template below. The Spartan-3A HDL Libraries Guide will be updated for a future design tools release and should be used at that time.

Solution

1

Verilog Instantiation Template:

// DSP48A : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (DSP48A_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// DSP48A: DSP Function Block
// Spartan-3A DSP
// Xilinx HDL Language Template, version 9.2i

DSP48A #(
.A0REG(0), // Enable=1/disable=0 first stage A input pipeline register
.A1REG(1), // Enable=1/disable=0 second stage A input pipeline register
.B0REG(0), // Enable=1/disable=0 first stage B input pipeline register
.B1REG(1), // Enable=1/disable=0 second stage B input pipeline register
.CARRYINREG(1), // Enable=1/disable=0 CARRYIN input pipeline register
.CARRYINSEL("CARRYIN"), // Specify carry-in source, "CARRYIN" or "OPMODE5"
.CREG(1), // Enable=1/disable=0 C input pipeline register
.DREG(1), // Enable=1/disable=0 D pre-adder input pipeline register
.MREG(1), // Enable=1/disable=0 M pipeline register
.OPMODEREG(1), // Enable=1/disable=0 OPMODE input pipeline register
.PREG(1), // Enable=1/disable=0 P output pipeline register
.RSTTYPE("SYNC") // Specify reset type, "SYNC" or "ASYNC"
) DSP48A_inst (
.BCOUT(BCOUT), // 18-bit B port cascade output
.CARRYOUT(CARRYOUT), // 1-bit carry output
.P(P), // 48-bit output
.PCOUT(PCOUT), // 48-bit cascade output
.A(A), // 18-bit A data input
.B(B), // 18-bit B data input (can be connected to fabric or the BCOUT of an adjacent DSP48A)
.C(C), // 48-bit C data input
.CARRYIN(CARRYIN), // 1-bit carry input signal (can be connected to fabric or the CARRYOUT of an adjacent DSP48A)
.CEA(CEA), // 1-bit active high clock enable input for A input registers
.CEB(CEB), // 1-bit active high clock enable input for B input registers
.CEC(CEC), // 1-bit active high clock enable input for C input registers
.CECARRYIN(CECARRYIN), // 1-bit active high clock enable input for CARRYIN registers
.CED(CED), // 1-bit active high clock enable input for D input registers
.CEM(CEM), // 1-bit active high clock enable input for multiplier registers
.CEOPMODE(CEOPMODE), // 1-bit active high clock enable input for OPMODE registers
.CEP(CEP), // 1-bit active high clock enable input for P output registers
.CLK(CLK), // Clock input
.D(D), // 18-bit B pre-adder data input
.OPMODE(OPMODE), // 8-bit operation mode input
.PCIN(PCIN), // 48-bit P cascade input
.RSTA(RSTA), // 1-bit reset input for A input pipeline registers
.RSTB(RSTB), // 1-bit reset input for B input pipeline registers
.RSTC(RSTC), // 1-bit reset input for C input pipeline registers
.RSTCARRYIN(RSTCARRYIN), // 1-bit reset input for CARRYIN input pipeline registers
.RSTD(RSTD), // 1-bit reset input for D input pipeline registers
.RSTM(RSTM), // 1-bit reset input for M pipeline registers
.RSTOPMODE(RSTOPMODE), // 1-bit reset input for OPMODE input pipeline registers
.RSTP(RSTP) // 1-bit reset input for P output pipeline registers
);

// End of DSP48A_inst instantiation

2

VHDL Instantiation Template:

-- DSP48A : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (DSP48A_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.

-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- DSP48A: DSP Function Block
-- Spartan-3A DSP
-- Xilinx HDL Language Template, version 9.2i

DSP48A_inst : DSP48A
generic map (
A0REG => 1, -- Enable=1/disable=0 first stage A input pipeline register
A1REG => 1, -- Enable=1/disable=0 second stage A input pipeline register
B0REG => 1, -- Enable=1/disable=0 first stage B input pipeline register
B1REG => 1, -- Enable=1/disable=0 second stage A input pipeline register
CARRYINREG => 1, -- Enable=1/disable=0 first stage A input pipeline register
CARRYINSEL => "CARRYIN", -- Specify carry-in source, "CARRYIN" or "OPMODE5"
CREG => 1, -- Enable=1/disable=0 C input pipeline register
DREG => 1, -- Enable=1/disable=0 D pre-adder input pipeline register
MREG => 1, -- Enable=1/disable=0 M pipeline register
OPMODEREG => 1, -- Enable=1/disable=0 OPMODE input pipeline register
PREG => 1, -- Enable=1/disable=0 P output pipeline register
RSTTYPE => "SYNC") -- Specify reset type, "SYNC" or "ASYNC"
port map (
BCOUT => BCOUT, -- 18-bit B port cascade output
CARRYOUT => CARRYOUT, -- 1-bit carry output
P => P, -- 48-bit output
PCOUT => PCOUT, -- 48-bit cascade output
A => A, -- 18-bit A data input
B => B, -- 18-bit B data input (can be connected to fabric or the BCOUT of an adjacent DSP48A)
C => C, -- 48-bit C data input
CARRYIN => CARRYIN, -- 1-bit carry input signal (can be connected to fabric or the CARRYOUT of an adjacent DSP48A)
CEA => CEA, -- 1-bit active high clock enable input for A input registers
CEB => CEB, -- 1-bit active high clock enable input for B input registers
CEC => CEC, -- 1-bit active high clock enable input for C input registers
CECARRYIN => CECARRYIN, -- 1-bit active high clock enable input for CARRYIN registers
CED => CED, -- 1-bit active high clock enable input for D input registers
CEM => CEM, -- 1-bit active high clock enable input for multiplier registers
CEOPMODE => CEOPMODE, -- 1-bit active high clock enable input for OPMODE registers
CEP => CEP, -- 1-bit active high clock enable input for P output registers
CLK => CLK, -- Clock input
D => D, -- 18-bit B pre-adder data input
OPMODE => OPMODE, -- 8-bit operation mode input
PCIN => PCIN, -- 48-bit P cascade input
RSTA => RSTA, -- 1-bit reset input for A input pipeline registers
RSTB => RSTB, -- 1-bit reset input for B input pipeline registers
RSTC => RSTC, -- 1-bit reset input for C input pipeline registers
RSTCARRYIN => RSTCARRYIN, -- 1-bit reset input for CARRYIN input pipeline registers
RSTD => RSTD, -- 1-bit reset input for D input pipeline registers
RSTM => RSTM, -- 1-bit reset input for M pipeline registers
RSTOPMODE => RSTOPMODE, -- 1-bit reset input for OPMODE input pipeline registers
RSTP => RSTP -- 1-bit reset input for P pipeline registers
);

-- End of DSP48A_inst instantiation
AR# 25096
Date Created 09/04/2007
Last Updated 09/04/2008
Status Archive
Type General Article