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AR# 25124

LogiCORE Initiator/Target v3.162 for PCI64 - The cfg.v(vhd) file provided with the core contains conflicting bit assignments


The HDL module generated with the core called "cfg.v(vhd)," which controls the bit assignments for the core CFG vector, contains conflicting bit assignments. This file is located in the "<core_name>\<hdl>\src\xpci" directory. The file contains the following code near the end of the module:

// Do Not Modify

assign CFG[241] = `DISABLE ;

assign CFG[242] = `DISABLE ;

assign CFG[243] = `DISABLE ;

These assign statements conflict with other assign statements for the CFG[241], CFG[242], and CFG[243] bits in the Base Address Register setting area of the same module.


To remedy this issue, the three assign statement lines listed in the "cfg.v(vhd)" file in the "Do Not Modify" section should either be removed our commented out.

A permanent fix for this will be included in IP Update 1 for ISE 9.2i.

AR# 25124
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article