When I simulate my System Generator design in Simulink, I receive the following warning message in the MATLAB command window:
"Warning: Inconsistent sample times. Sample time ([1, 0]) of signal driving input port 1 of 'my_design/delay 1' differs from the expected sample time ([100000, 0]) at this input port."
There are a couple different reasons these warnings can occur, in each of the following scenarios they can be safely ignored.
If a System Generator "Gateway In" block is driven by a continuous source, this warning might occur because the System Generator block must "sample" the input source which has an infinitely higher sample rate. This can be resolved by making the source a sampled source with an equivalent sample period to the System Generator block it drives.
Additionally these warnings can occur during simulation because of the way System Generator handles simulation scheduling during a simulation. For various reasons System Generator must use its own simulation scheduler. Because the Xilinx blocks plug into Simulink, a sample period by which Simulink will attempt to schedule activity must be provided. Since the scheduling for Xilinx blocks is handled by System Generator, a very large and arbitrary rate is passed to Simulink. This disparity causes the warnings during simulation; while during a model compile or model update, the warnings will not occur provided that the Simulink simulation scheduler is set to "Variable Step".