I get an error during clock DRCs similar to the following after I have created a Base System Builder design:
Performing Clock DRCs...
ERROR:MDT - Given value for Parameter RS232_Uart:C_CLK_FREQ - system.mhs line 184 is = 75000000, whereas the auto-computed value based on the specified frequency for top-level clock port is = 0.
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
ERROR:MDT - platgen failed with errors!
This problem has been fixed in the latest EDK 9.1i Service Pack, available at:
The first service pack containing the fix is EDK 9.1i Service Pack 2.