We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25134

9.1i EDK - The ML505 board reads the GPIO DIP switch in bit-reverse order


For a BSB-generated design, the generated TestApp_Peripheral software displays the settings of the GPIO DIP switch (SW8) in a bit-reverse order. The eight individual switches that make up DIP SW8 are numbered 1 to 8 from the left to right. If the DIP switches 1 to 4 are set to ON, and DIP switches 5 to 8 are set to OFF, running TestApp_Peripheral reports that the switches are set to 0xF instead of 0xF0.


This problem has been fixed in the latest EDK 9.1i Service Pack, available at:  


The first service pack containing the fix is EDK 9.1i Service Pack 2.

AR# 25134
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article