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AR# 25146

MPMC2 v1.8 - Fatal simulation error and hardware hangs when using registered DDR or unregistered discrete DDR2

Description


ISSUE is resolved with MPMC2 v1.9 release!



Simulation Failure

My simulation of MPMC2v1.8 with an unregistered discrete DDR2 indicates the following errors:



# system_tb.LO.data_task: at time 16047600.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period

# system_tb.LO.data_task: at time 16047600.0 ps ERROR: DQS bit 1 latching edge required during the preceding clock period

# system_tb.LO.data_task: at time 16047600.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period

# system_tb.LO.data_task: at time 16047600.0 ps ERROR: DQS_N bit 1 latching edge required during the preceding clock period



and then the data read from the DDR2 is incorrect and shifted. What is the problem, and is there a fix?



Hardware Failure

I have noticed that the mpmc2_0_InitDone signal is never asserted after the initial power up, and when my software application tries to access external memory, the system hangs. What is the problem, and is there a fix?

Solution


This is a known issue which is addressed with the patch found in this Answer Record.



You can download this patch, which resolves this issue and the issue indicated in (Xilinx Answer 25151).



This patch should be extracted to the MPMC2 install directory. It will overwrite the following files:



filename:data\

filename:data\mpmc2_mpd_master.txt

filename:data\mpmc2_top_level_v_master.txt

filename:data\master_source_files\

filename:data\master_source_files\hdl\

filename:data\master_source_files\hdl\verilog\

filename:data\master_source_files\hdl\verilog\mpmc2_core.v

filename:data\master_source_files\hdl\verilog\phy_calib_ddr2.v

filename:data\master_source_files\hdl\verilog\phy_io_ddr2.v

filename:data\master_source_files\hdl\verilog\phy_top_ddr2.v

filename:data\master_source_files\hdl\verilog\v4_phy_init_ddr1.v

filename:data\master_source_files\hdl\verilog\v4_phy_init_ddr2.v

filename:data\master_source_files\hdl\verilog\v4_phy_top.v



Click here for the patch:

http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?iLanguageID=1&ipoid=24332297&category=-1210766&filename=mpmc2_patch_20070504.zip&file=780
AR# 25146
Date Created 09/04/2007
Last Updated 11/12/2010
Status Archive
Type General Article