When using the PLL in a Virtex-5 design, the input delay path seems longer than I expected because the IO Delay is used. Should the tools be adding this delay and how do I prevent it?
When using the PLL, the default delay should not be inserted. This issue is scheduled to be fixed in ISE 10.1i.
To avoid this issue in the current tools, please use the IOBDELAY = "NONE" attribute on inputs that drive flops clocked off the PLL. For more information regarding the IOBDELAY attribute, please reference the Constraints Guide: