We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25155

9.1i Virtex-5 PLL - Should the inputs to flops clocked by a PLL be using Default IO Delay?


When using the PLL in a Virtex-5 design, the input delay path seems longer than I expected because the IO Delay is used. Should the tools be adding this delay and how do I prevent it?


When using the PLL, the default delay should not be inserted. This issue is scheduled to be fixed in ISE 10.1i.

To avoid this issue in the current tools, please use the IOBDELAY = "NONE" attribute on inputs that drive flops clocked off the PLL. For more information regarding the IOBDELAY attribute, please reference the Constraints Guide:


AR# 25155
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article