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AR# 25162

LogiCORE Endpoint Block Plus v1.3 for PCI Express - Release Notes and Known Issues for 9.1i IP Update 3 (9.1i_IP3)


This Release Notes and Known Issues Answer Record is for the LogiCORE Endpoint Block Plus v1.3 for PCI Express released in 9.1i IP Update 3, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).


General Information

License Requirements

As of the ISE 9.1i SP 2 IP Update 1 release, the LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license. To obtain the license visit the product lounge at:


ES Silicon

Please refer to (Xilinx Answer 24697) for information on targeting Virtex-5 engineering samples (ES) silicon with this core.

New Features

- Added all Virtex-5 LXT and SXT part and package UCF combinations

- Added simulation (MTI only) and PIO example design VHDL support

Bug Fixes

- CR 431927: Fixed issue with PCI ordering rules. When not using Completion Streaming, core will now correctly determine the next available packet type. In Completion Streaming mode, this is relaxed such that completions will still be read out-of-order, but Non-Posted and Posted transactions can still be ordered correctly.

- CR 433993: LTSSM state output signals not registered. LTSSM state output signals now registered to make timing closure easier.

- CR 434370: Fixed issue where user-side configuration read returns scrambled data for offset 0xF. User-side configuration read via the configuration management port returns scrambled data for configuration dword offset 0xF. The Integrated hard block for PCI Express internally maps the Interrupt Pin/Line (dword offset 0xF) to the upper reserved bits of the Capabilities Pointer(dword offset 0xD). If the user reads address 0xF, they will get the Int Pin/Line fields in the upper bits. The Block Plus core now descrambles the dword when this happens, to realign the Interrupt Pin/Line to the lower bits, where they are specified.

- CR 434724: Fixed warm reset issue. Problem fixed where a warm reset would cause the core not to respond to some memory apertures specified in CORE Generator.

Known Issues

- Refer to the "readme_pcie_blk_plus.txt" file delivered with the core for known issues at the time of the release.

- Some LX330T x1, x4, and x8 designs might not meet timing with the default MAP and PAR settings. In order to obtain timing closure, designers might be required to use

multiple PAR seeds and/or floorplanning. Using Multi-Pass Place and Route (MPPR), designers can try multiple cost tables in order to meet timing. For more information on using MPPR, see the Development System Reference Guide in the Software Manuals found at:


Designers might also have to floorplan and add advanced placement constraints for both their design and the core to meet timing.

- Core Receive Flow Control Credit Available signals are unavailable; trn_rfc_{p,np}h_av[7:0] and trn_rfc_{p,np}d_av[11:0] are not indicating correct values. These signals are considered informational only and are not critical for correct operation of Endpoint application.

- When generating a core, CORE Generator will display "WARNING:coreutil - coreutil:39 - Parsing of check license val <> failed." This warning can be safely ignored. The core will still be generated.

- See (Xilinx Answer 24174) if you receive an error stating "ERROR:coreutil - Failure to generate output products" in CORE Generator.

- See (Xilinx Answer 25216) regarding duplicated Block Plus core entries in the CORE Generator taxonomy list.

AR# 25162
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article