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AR# 25165

LogiCORE Initiator/Target v4.3 for PCI - Release Notes and Known Issues for 9.1i IP Update 3 (9.1i_IP3)


This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target v4.3 for PCI, released in 9.1i IP Update 3, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).


General Information

The LogiCORE PCI v4.3 supports Virtex-5 and newer architectures only. For all other devices, use the v3.162 PCI Core. For more information on this core, refer to (Xilinx Answer 25164).

New Features

- XC5VLX110/T and XC5VSX70T device support

- XC5VLX50/T design files updated for ISE 9.1i Service Pack 3

Bug Fixes

- CR 433609: Fixed issue where GUI allowed user to choose illegal combinations of regional vs. global clocking with 33 MHz and 66 Mhz cores.

- CR 434037: Fixed simulate_ncsim.bat/sh file to ensure NCELAB correctly annotates VHDL timing simulations with SDF data.

- CR 435597: Fixed GUI problem that allowed users to target the 66 MHz core to a -1 device even though 66 MHz is only supported in -2.

- CR 436627: Fixed REQ64# internal connection logic.

Known Issues

- Please refer to the release notes text file delivered with the core for known issues at the time of the release.

- The name of this core has changed in v4.3, so if the user attempts to port old XCO files to v4.3, the following setting needs to be changed:

SELECT PCI_64-bit_Interface_LogiCore family Xilinx,_Inc. 4.2


SELECT LogiCORE_64-bit_Initiator/Target_for_PCI_(Virtex-5_only) family Xilinx,_Inc. 4.3

- Improvements to the GUI also necessitate changes to the following variable settings when porting old XCO files:

CSET pci_33mhz=true -> CSET bus_standard=PCI_33MHz

CSET pci_66mhz=true -> CSET bus_standard=PCI_66MHz

All "false" settings for pci_33mhz, pcix_66mhz, and pcix_133mhz should be removed. Also, the bus_mode setting is no longer used, as it is implied by the bus_standard setting.

These changes ensure that only one bus standard is selected whenever the core is generated.

AR# 25165
Date 12/15/2012
Status Active
Type General Article
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