We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25167

LogiCORE Initiator/Target v6.3 for PCI-X - Release Notes and Known Issues for 9.1i IP Update 3 (9.1i_IP3)


This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target v6.3 for PCI-X released in 9.1i IP Update 3, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24847).


General Information

The LogiCORE PCI v6.3 supports Virtex-5 and newer architectures only. For all other devices, use the v5.162 PCI-X Core. For more information on this core, refer to (Xilinx Answer 25166).

New Features

- XC5VLX110/T and XC5VSX70T device support

- XC5VLX50/T design files updated for ISE 9.1i Service Pack 3

Bug Fixes

- CR 433817: Fixed UCF files for PCI-X mode to use correct IOBDELAY constraint. Constraint has been corrected to: IOBDELAY=NONE

- CR 434037: Fixed simulate_ncsim.bat/sh file to ensure NCELAB correctly annotates VHDL timing simulations with SDF data.

- CR 436622: In -1 speedgrade clock period on DCM input clock violated upper frequency limit of the DCM. In the -1 speed grade, the Virtex-5 DCM is rated to a 120 MHz input clock in low-frequency mode. Thus, the DCM would be over clocked in PCI-X 133 mode. (The DCM's high-frequency mode could not be used because its range of 120-450 MHz does not fully encapsulate the PCI-X range of 50-133 MHz.) To remedy this, the DCM has been replaced by a PLL, rated to 710 MHz.

Known Issues

- Please refer to the release notes text file delivered with the core for known issues at the time of the release.

-The name of this core has changed in v6.3, so if the user attempts to port old XCO files to v6.3, the following setting needs to be changed:

SELECT PCI-X_Interface family Xilinx,_Inc. 6.3


SELECT LogiCORE_Initiator/Target_for_PCI-X_(Virtex-5_only) family Xilinx,_Inc. 6.3

- Improvements to the GUI also necessitate changes to the following variable settings when porting old XCO files:

CSET pci_33mhz=true -> CSET bus_standard=PCI_66MHz

CSET pcix_66mhz=true -> CSET bus_standard=PCI-X_66MHz

CSET pcix_133mhz=true -> CSET bus_standard=PCI-X_133MHz

All "false" settings for pci_33mhz, pcix_66mhz, and pcix_133mhz should be removed. The bus_mode setting is also no longer used, as it is implied by the bus_standard setting.

These changes ensure that only one bus standard is selected whenever the core is generated.

AR# 25167
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article