UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25169

9.1i IP Update 3 CORE Generator IP-DSP - What's New and Known Issues List

Description

Keywords: ISE, LogiCORE, Binary Counter, Comparator, Direct Digital Synthesis, DDC, Distributed Arithmetic FIR Filter, FIR Compiler, MAC FIR, MACC FIR, Multiplier Generator, DVB S2 FEC Encoder, FFT, Floating-point, Divider Generator, Pipelined Divider, RAM Based Shift Register, TCC Decoder 3GPP, CTC Encoder 802.16e, LDPC Encoder 802.16, Viterbi

This Answer Record for the CORE Generator contains the IP-DSP What's New and Known Issues addressed in the 9.1i IP Update 2 and 9.1i Update 3, and contains the following:

- New Features
- Bug Fixes
- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 24847).

Solution

What's New in 9.1i IP Update 3

LogiCORE Convolution Encoder v6.1
New Features in v6.1
- Support added for Spartan-3A DSP

Bug Fixes in v6.1
- None


LogiCORE Direct Digital Synthesizer (DDS) Compiler
The Direct Digital Synthesizer Compiler LogiCORE replaces the Direct Digital Synthesizer core as well as all previous versions of the Direct Digital Synthesizer Compiler LogiCore and should be used in all new designs.

New Features in v2.0
- Several improvements to maximum clock rate or resource utilization compared to version 1.1
- Separation of A port into REG_SELECT and ADDR to allow optional port behavior

Bug Fixes in v2.0
- CR - Symbol does not reflect correct port widths


LogiCORE DVB S2 FEC Encoder v1.3
New Features in v1.3
- Support added for Spartan-3A DSP
- Addition of pilot and frame bits to rate input and output. Bits can be used for general purpose control signaling as data passes through the core.

Bug Fixes in v1.3
- None


LogiCORE Reed-Solomon Decoder v6.1
New Features in v6.1
- Support added for Spartan-3A DSP devices

Bug Fixes in v6.1
- CR 431627 - Evaluation version generated even with full license in place


LogiCORE Reed-Solomon Encoder v6.1
New Features in v6.1
- Support added for Spartan-3A DSP devices
- New, easier to use GUI

Bug Fixes in v6.1
- None


LogiCORE 3GPP Turbo Decoder v3.1
New Features in v3.1
- Spartan-3A DSP support

Bugs Fixed in v3.1
- CR 436068: Incorrect behavior of ND input. ND must be held high for 2 extra clock cycles after RFD is deasserted. See (Xilinx Answer 24107).


LogiCORE Viterbi Decoder
New Features in v6.1
- Support added for Spartan-3A DSP

Bug Fixes in v6.1
- CR 431791: For constraint length 9, the BER performance is not optimal at high SNR the BER plots shows an error floor
- CR 435735: In serial mode, if the ND signal is not periodic, the Viterbi Decoder v6.0 does not work correctly


Known Issues in 9.1i IP Update 2

None


Known Issues in Existing IP

LogiCORE Add Sub v7.0
- Why is my output result one less than the expected result? See (Xilinx Answer 23933).

LogiCORE CIC v3.0
- The CIC Filter v3.0 exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).
- The CIC Filter v3.0 reset. See (Xilinx Answer 20187).
- The CIC Filter v3.0 input and output date format. See (Xilinx Answer 17210).

LogiCORE Complex Multiplier v2.1
- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).

LogiCORE CORDIC v3.0
- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).
- LogiCORE CORDIC v3.0 - Why does the behavioral simulation for the CORDIC square root mode require four extra clocks after asserting the ND signal before the data will be processed? See (Xilinx Answer 23934).

LogiCORE Distributed Arithmetic FIR (DA FIR) Filter v9.0
- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).
- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).
- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).
- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE Digital Down Convertor (DDC)
- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE DDS Compiler v1.1
- Why is the behavioral simulation output incorrect when using the structural simulation model? See (Xilinx Answer 24316).
- Why are the outputs on the DDS CORE Generator GUI always displayed as 32-bits wide? See (Xilinx Answer 24410).
- Why are the outputs on the DDS schematic symbol always displayed as 32-bits wide? See (Xilinx Answer 24412).

LogiCORE 1024-pt FFTv1.0
- The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations. See (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0
- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0
- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0
- A Verilog model is not available for the FFT Core. See (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0
- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).

LogiCORE FFT
- Simulation of all fixed netlist FFT (64, 256, 1024) Cores generates many warnings. See (Xilinx Answer 14861).
- Information on output connections to the fixed netlist FFT (64, 256, 1024) Cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).

LogiCORE Fast Fourier Transform (xFFT) v3.2/patch 1
- Large FFT point size generation times. See (Xilinx Answer 21988).
- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).
- First frame after multi-cycle reset might be incorrectly marked as valid. See (Xilinx Answer 24436).



LogiCORE FIR Compiler v3.0
- I cannot use the multi-column support when my coefficients are symmetrical. See (Xilinx Answer 22936).
- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).
- Why does FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when attempting to customize them on Solaris? See (Xilinx Answer 24317).
- Distributed Arithmetic Filter Architecture:
-- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).
-- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).
-- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).
- Multiply Accumulator Filter Architecture for all devices other than Virtex-4 and Virtex-5:
-- Why does my single-rate MAC FIR filter fail to generate, giving me an empty or missing netlist and "ERROR:sim - NgdBuild:153" or "ERROR:NgdBuild:604"? See (Xilinx Answer 22706).
-- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).
-- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).
-- COE errors reported in wrong format. See (Xilinx Answer 14202).
-- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).


LogiCORE Floating-Point Operators v3.0
- Why do I not see a resource estimation graph for my Floating Point operator function? See (Xilinx Answer 24039).
- Why do FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when I attempt to customize them on Solaris? See (Xilinx Answer 24317).

LogiCORE MAC v4.0
- Virtex-4 maximum number of cycles. See (Xilinx Answer 21511).
- When I set up my Multiply Accumulate v4.0 Core to have a wide input (e.g., 24x16) and use an output that is less than full precision, why is there no activity on the output of my core during simulation? See (Xilinx Answer 24096).

LogiCORE MAC FIR v5.1
- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).
- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).
- COE Errors reported in wrong format. See (Xilinx Answer 14202).
- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).
- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).



LogiCORE Multiplier Generator v10.0
- Why does my Virtex-5 LUT-based multiplier give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware when I do not use any pipelining? See (Xilinx Answer 23705).
- How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input? See (Xilinx Answer 23599).
- Why can I not add handshaking signals to my multiplier? See (Xilinx Answer 23598).
- How do I generate a multiplier with an asynchronous clear? See (Xilinx Answer 23600).


LogiCORE Pipelined Divider v3.0
- How to do I perform a Verilog behavioral simulation? See (Xilinx Answer 20615).

LogiCORE RAM-based Shift Register v9.0
- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).
- Why is the LogiCORE RAM-based Shift Register v9.0 almost 10 times larger than the LogiCORE RAM-based Shift Register v8.0, when targeting Virtex or Spartan-II? See (Xilinx Answer 23696).

LogiCORE Turbo Product Code Encoder and Decoder (TPC)
- How can I get the TPC to compile using XST, without incurring MAP Pack error: "ERROR:Pack:679"? See (Xilinx Answer 22258).
- Why does the reset need to be applied for the code to be changed? See (Xilinx Answer 24298).
- Why does the OutputRDY signal Remain high for six clock cycles after the output FIFO is empty? See (Xilinx Answer 24299).

AR# 25169
Date Created 09/04/2007
Last Updated 03/30/2009
Status Archive
Type General Article