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AR# 25181

9.1i EDK SP2 - mch_opb_emc_v1_01_a post-PAR simulation fails with timing error

Description

I receive a post-PAR simulation failure with the mch_opb_emc_v1_01_a Core, as follows:  

 

"** ERROR: 37470NS 1.4.0 OPB_RETRY: OPB_RETRY AND OPB_XFERACK ACTIVE IN THE SAME CYCLE.  

 

/TOOLS/XGS/PERL/5.8.5/BIN/PERL /PROJ/XTOOLS/SVAUTO2/FLOWS/EDKIP/V2_1/EDKIP.PL -CADSET_XILINX J.33.3_EDK_J_SP1.3 -CADSET_EDK EDK_J_SP1.3_J.33.3 -TC /PROJ/XTCREPO/EDKSATHISHV/_TCASE/EDKIPTEST/MCH_OPB_EMC_V1_01_A/VIRTEX2P/MOE_MAX55766_0/INPUT -CADSET_MODELSIM 6.1E -SIMULATION 1 -DEBUGLEVEL 6 -SIMULATOR MODELSIM -FAMILY VIRTEX2P -DEVICE XC2VPX20 -PACKAGE FF896 -SPEEDGRADE 7 "

Solution

This is due to a mismatch of memory bank addresses in the VHDL files. 

 

This problem has been fixed in the latest EDK 9.1i Service Pack, available at:  

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 9.1i Service Pack 2.

AR# 25181
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article