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Virtex-5 DCM - The DCM does not deskew the clock properly for both system synchronous and source synchronous designs

AR# 25192

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Topic Virtex-5 Family
Last Updated 07/02/2007
Status Active
Description

Keywords: System, Synchronous, timing, DCM, patch

When the Virtex-5 DCM is set to the default mode of System Synchronous (DESKEW_ADJUST = SYSTEM_SYNCHRONOUS), or Source Synchronous (DESKEW_ADJUST = SOURCE_SYNCHRONOUS), the DCM does not adjust the delay on the clock line properly in hardware. Timing on the board might fail even though timing analysis shows the design meets timing specifications.

Solution

A patch available for 9.1i Service Pack 3 fixes this problem.

Extract the following file into your Xilinx install directory:
http://www.xilinx.com/txpatches/pub/utilities/fpga/25192.zip

The DCM DESKEW_ADJUST issue patch will be included in the design tools in ISE 9.2i Service Pack 1.
 
 
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