When the Virtex-5 DCM is set to the default mode of System Synchronous (DESKEW_ADJUST = SYSTEM_SYNCHRONOUS), or Source Synchronous (DESKEW_ADJUST = SOURCE_SYNCHRONOUS), the DCM does not adjust the delay on the clock line properly in hardware. Timing on the board might fail even though timing analysis shows the design meets timing specifications.
A patch available for 9.1i Service Pack 3 fixes this problem.
Extract the following file into your Xilinx install directory:
The DCM DESKEW_ADJUST issue patch will be included in the design tools in ISE 9.2i Service Pack 1.