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AR# 25308

9.2i Timing Analysis Virtex-5 - In DDR component, only the rising or falling OFFSET constraints are analyzed


I constrained my ODDR and IDDR components with rising and falling OFFSET constraints. During the analysis, only the rising or falling OFFSET constraints are analyzed. When will this problem be fixed?


This issue is scheduled to be fixed in the next major release of the design tools.

To work around this issue, use the same values from the rising edge elements for the falling edge elements, or the other way around.

AR# 25308
Date Created 09/04/2007
Last Updated 01/18/2010
Status Archive
Type General Article