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AR# 25319

LogiCORE RapidIO v4.1 - Using the example design, some of the ireq ports are not connected properly


When using the Example design provided with the core, several of the ireq ports are not connected properly. Also, when running simulation, warning or errors similar to the following might occur: 


"# ** Warning: (vsim-3015) ../../example_design/srio_v4_1_x1_dl_top.v(353): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'ireq_db_info'. 

 # Region: /ep_tb/ep/user_top"


This issue has been fixed in v4.2 of the Serial RapidIO. 


If you are still using v4.1 of Serial RapidIO, and you want to send a doorbell or messages, you must use following work-around. In the Example Design directory, open the top-level wrapper file "<component_name>_top.v" and edit the following lines: 


Change the following lines: 


.ireq_db_info (ireq_db_info), 

.ireq_msg_len (ireq_msg_len), 

.ireq_msg_seg (ireq_msg_seg), 

.ireq_mbox (ireq_mbox), 

.ireq_letter (ireq_letter), 


To the following: 


.ireq_db_info (ireq_db_info_i), 

.ireq_msg_len (ireq_msg_len_i), 

.ireq_msg_seg (ireq_msg_seg_i), 

.ireq_mbox (ireq_mbox_i), 

.ireq_letter (ireq_letter_i),

AR# 25319
Date 05/21/2014
Status Archive
Type General Article
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