UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25321

9.2i Timing Analysis Virtex-5 - IDDR/ODDR are not analyzed for OFFSET IN/OUT constraints with RISING/FALLING timegrps

Description

When I run timing analysis on my design with IDDR and ODDR components, OFFSET IN and OFFSET OUT constraints, and the RISING and FALLING time group, one of the OFFSET constraints has 0 items analyzed. When is this going to be fixed?

Solution

This problem has been fixed in the latest 9.2i Service Pack available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 9.2i Service Pack 1.

AR# 25321
Date Created 09/04/2007
Last Updated 01/18/2010
Status Archive
Type General Article