UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25325

9.2i Floorplanner - An error occurs when writing DSP48 component LOC constraints

Description

When I try to lock down the DSP48 component in a Virtex-5 design, the constraint written to the UCF is "DSP48E_XnYn" instead of "DSP48_XnYn".  

 

When is this issue going to be fixed?

Solution

This problem has been fixed in the latest 9.2i Service Pack available at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 9.2i Service Pack 1.

AR# 25325
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article