UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25334

9.2i EDK - Error: "ERROR:Place:635 - A clock IOB / DCM clock component pair have been found that are not placed at an optimal clock IOB/DCM site pair"

Description

In a design for ML405, the included peripherals are RS232, LEDs_4Bit, Leds_Positions, DDR_SDRAM_64Mx32, FLASH_2Mx32, and PLB BRAM. When I implement my design, the following error at MAP stage occurs:

"ERROR:Place:635 - A clock IOB / DCM clock component pair have been found that are not placed at an optimal clock IOB /DCM site pair. The clock IOB component <fpga_0_DDR_CLK_FB> is placed at site <D13>. And the corresponding DCM component <DCM_AUTOCALIBRATION_dcm_1/dcm_1/Using_DCM_ADV.DCM_ADV_INST/dcm_1/dcm_1/Using_DCM_ADV.DCM_ADV_INST> is placed at site <DCM_ADV_X0Y0>. The clock IO site can use the fast path between the IOB and DCM if the IOB & DCM are placed/locked in the same half of the device (TOP or BOTTOM). If this sub optimal condition is acceptable for this design, you may set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue."

Solution

To work around this problem, you will need to manually lock down the DCM.

This issue will be fixed in a future release of the tool.

AR# 25334
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article