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AR# 25346

MPMC2 v1.9 - Migrating from MPMC2 v1.7 to MPMC2 v1.9

Description

I am currently using MPMC2 version 1.7. How can I transition to using MPMC2 v1.9?

Solution


Refcore Updates:



1. Put the old refcore into mpmc2 v1.9 data/refcores directory. To generate a new pcore, you have to update your old refcore. If you do not have a refcore, use your "control.txt" to create one by following the instructions in (Xilinx Answer 23595).



2. Edit your refcore with your favorite text editor to make these changes:



Find line: #define GUI_VERSION 1.7

Change To: #define GUI_VERSION 1.9



Find line: #define mem_set_reg_dimms

Add below: #define enable_ecc 0



3. Load the mpmc2_gui executable, load your refcore, reload your memory part and create pcore. NOTE: If there are any problems here, you must create a new pcore by re-entering your configuration into the GUI.



4. Copy this pcore to your project directory.



5. Use the "control.txt" from this new pcore to use as your new refcore. It will have the rest of the changes that were not hand modified above.



MHS Updates:



1. The following port connections are no longer needed by the MPMC and can be removed:



a. MPMC2_0_Clk0_2X

b. PORT MPMC2_0_Clk_Cal

c. MPMC2_0_Clk_Mem



2. If your design has PLB/ISPLB/DSPLB ports, remove all references to:



a. C_[DSPLB|ISPLB|PLB]_[PORT_NUM]_PLB MID_WIDTH

b. C_[DSPLB|ISPLB|PLB]_[PORT_NUM]_NUM_MASTER



3. Remove all port reset assignments from all the ports. You should keep only MPMC2_0_Rst PORT connected up in the MPMC in "system.mhs." All other resets can be removed from "system.mhs."



4. Remove Clock PORT assignments for ISPLB, DSPLB, MPLB, SPLB, MOPB, SOPB, and XCL. These clock signals are now automatically made based on the bus connected to the MPMC. (NOTE: You must retain the clock assignments for DCR interfaces and CDMAC.)



5. Change MPMC2_0_DDR[2]_DM to MPMC2_0_DDR[2]_DM_O.



6. Update the external port connection for the DM pin from IO to O.



7. Ensure that all external port names have the same wire names connecting to MPMC2.



8. C_MPMC2_0_MEM_DQS_MATCHED is now a constant value and should be removed.



9. Update:



From: PARAMETER HW_VER = 1.05.a

To: PARAMETER HW_VER = 2.10.a





UCF Updates:



The following modifications must be made to ALL UCF files.



1. MPMC2_0_DDR2_Clk_O must have an IOSTANDARD = DIFF_SSTL[2|18]_II



2. MPMC2_0_DDR2_Clk_n_O must have an IOSTANDARD = DIFF_SSTL[2|18]_II



3. MPMC2_0_DDR2_DQS must have an IOSTANDARD = DIFF_SSTL[2|18]_II[_DCI] if using differential dqs



4. MPMC2_0_DDR2_DQS_n must have an IOSTANDARD = DIFF_SSTL[2|18]_II[_DCI] if using differential dqs



If you fail to perform these changes, you will receive the following error:



"ERROR:Pack:1107 - Unable to combine the following symbols into a single IOBM

component:

PAD symbol "o_ddr0_clk_p<1>" (Pad Signal = o_ddr0_clk_p<1>)

BUFINV symbol

"mpmc2_ddr2_0/mpmc2_ddr2_0/mpmc2_core_0/gen_v4_phy_top.mpmc2_phy_if_0/iobs_0/

infrastructure_iobs_00/gen_oddr_clk[1].OBUFDS/OBUFDS" (Output Signal = o_ddr0_clk_p<1>)

Each of the following constraints specifies an illegal physical site for a component of type IOBM:

Symbol "o_ddr0_clk_p<1>" (LOC=AK34)

Please correct the constraints accordingly."



5. If you have previously had IDELAYCTRL's that were LOC, the path to the IDELAYCTRL's has changed, so you must change the path in your UCF file. The changes to the IDELAY controller logic and implementation are outlined on page 32 of the MPMC Users Guide (UG253).



For example, if you have N IDELAYCTRL's.



From:

INST <path_to_mpmc2>/*/idelayctrl0 LOC=IDELAYCTRL_X?Y?

INST <path_to_mpmc2>/*/idelayctrl1 LOC=IDELAYCTRL_X?Y?

INST <path_to_mpmc2>/*/idelayctrl<N> LOC=IDELAYCTRL_X?Y?



To:

INST <path_to_mpmc2>/gen_instantiate_idelayctrls[0].idelayctrl0 LOC=IDELAYCTRL_X?Y?

INST <path_to_mpmc2>/gen_instantiate_idelayctrls[1].idelayctrl0 LOC=IDELAYCTRL_X?Y?

INST <path_to_mpmc2>/gen_instantiate_idelayctrls[N].idelayctrl0 LOC=IDELAYCTRL_X?Y?



Note: 'N' is a number from 0 to the number of IDELAYCTRL in your system (Xilinx Answer 24644).





NPI Considerations:



1. Change your bus interface from:



BUS_INTERFACE BUS = MPMC2_PIM_0, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF

To

BUS_INTERFACE BUS = MPMC2_PIM_0, BUS_STD = NPI, BUS_TYPE = INITIATOR



2. Add these ports to your bus on your NPI module:



PORT PI_InitDone = InitDone, DIR = I, BUS = MPMC2_PIM_0

PORT PI_RdModWr = RdModWr, DIR = O, BUS = MPMC2_PIM_0

PORT PI_RdFIFO_Latency = RdFIFO_Latency, DIR = I, VEC = [1:0], BUS = MPMC2_PIM_0

PORT PI_WrFIFO_Empty = WrFIFO_Empty, DIR = I, BUS = MPMC2_PIM_0



3. For detailed descriptions and usage instructions, please see the MPMC2 User Guide (Ug253).





Code/Linker Considerations:



1. The first 0xFF addresses are reserved for memory calibration and initialization. Code placed in this area will get corrupted upon reset. Therefore, it is recommended that you do not place any downloadable code in this area when creating your linker script. Typically, after your code is downloaded into the memory, a reset is issued, which would corrupt you code if placed in this area.
AR# 25346
Date Created 09/04/2007
Last Updated 11/12/2010
Status Archive
Type General Article