We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25360

LogiCORE Distributed RAM v3.3 - DPRa Reg clocked incorrectly in certain Dual Port RAM configurations


As seen in Figure 6 of DS322, Qdpo_clk drives DPRa Reg out, as well as DPO. Qdpo_clk is only implemented when output registers are enabled. If this option is deselected, qdpo_clk is not implemented and DPRa Reg is driven by CLK


DPRa Reg should be clocked by QDPO_CLK when Dual Port Address input registers are used. Currently, DPRa Reg is clocked by CLK unless Output Registers are used. CR# 440076 has been filed on this issue to have DPRa Reg clocked by QDPO_CLK regardless of whether output registers are implemented.

AR# 25360
Date Created 09/04/2007
Last Updated 05/22/2014
Status Archive
Type General Article