We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25361

LogiCORE Distributed RAM v3.3 - Figure 6 of Distributed RAM Data Sheet (DS322) shows incorrect clocking for QDPO_CE and QSPO_CE


Figure 6 of DS322 shows incorrect clocking for the clock enable registers QDPO_CE and QSPO_CE.


QDPO_CE should be clocked by QDPO_CLK, and QSPO_CE should be clocked by CLK, but the figure in the data sheet shows the opposite. CR #440140 has been filed and the datasheet will be updated in the next release showing the correct clocking scheme.

AR# 25361
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked