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AR# 25362

LogiCORE Endpoint v3.5 and v1.7 PIPE for PCI Express - MSI vector field in GUI is not correctly translated to output netlist

Description

The Endpoint v3.5 and v1.7 PIPE for PCI Express CORE Generator customization GUI does not correctly translate the number of MSI vectors requested in the output netlist.

Solution

Xilinx Endpoint and Endpoint PIPE solutions for PCI Express support up to 32 MSI vectors. The v1.7 PIPE and v3.4 Endpoint solutions customization GUI does not correctly translate the number of MSI vectors requested (page 6 of 8) into the core netlist. Both the generated netlist and generated simulation model display the error.

This issue will be fixed in the next release of the core. To work around this issue, edit the .xco file and regenerate the core.

Change the line below to request more than one vector:

CSET multiple_message_capable=1_vector

Possible implementations:

CSET multiple_message_capable=1_vector

CSET multiple_message_capable=2_vectors

CSET multiple_message_capable=4_vectors

CSET multiple_message_capable=8_vectors

CSET multiple_message_capable=16_vectors

CSET multiple_message_capable=32_vectors

After editing the XCO, regenerate the core. Open the CORE Generator Project that generated the original core. Click on the "Generated IP" tab and select the core for PCI Express generated earlier. Click on "Regenerate (Under Current Project Settings)". CORE Generator loads the edited XCO file and generates a correct core netlist and simulation model.

AR# 25362
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article