9.1i ISE - Designs containing IP cores fail to synthesize with either Synplify Pro or Precision
Description
Keywords: Verilog, Windows, CORE Generator
When an existing IP core (<core_name>.xco) is added to a project, using Project -> Add Copy of Source, the .xco file and all of the related files (.ngc, .edn. .v, .vhd, etc.) are copied to the project directory and added to or "registered" by the project as needed. However, in this case, related IP files are not being properly "registered" and the netlist (.ngc or .edn) file is being sent to the third party synthesis tool instead of the core wrapper (.v or .vhd) file. Because Verilog requires the port declaration of an instantiated module, and Synplify and Precision do not parse the netlist file for this information, they fail with a message about an unresolved module. The following error is reported by Precision at the Project Navigator console:
"# Error: Found unresolved black-boxes in the design"
Solution
To fix the issue you can use one of the following:- Run Regenerate Core on .xco source after adding it to the project.
- Run XST - Synthesis first and then change the project synthesis tool to Precision.
- Remove the .xco file from the project and add the .v or .vhd file in its place.
- Use VHDL as the intermediate language for IP cores as follows:
1. Select the core in the sources window.
2. Right-click on COREGen -> View HDL Functional Model in the process window.
3. Select properties.
This problem has been fixed in the latest 9.2i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 9.2i Service Pack 1.