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AR# 25380

9.1i Virtex-5 MAP - "ERROR:Place:907 - Placer failed to find a location for a regional clock load"


My design fails with the following error even though I believe that my Regional Clock nets are not improperly constrained. What could be the problem?

"ERROR:Place:907 - Placer failed to find a location for a regional clock load. It is partially caused by user constraint
on following component group:
To debug your design with partially routed design, please try to allow map/placer to finish the execution (by setting
environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1)."

NOTE: This error message can occur for the case of any improperly constrained regional clock load. This Answer Record addresses the specific mapping issue of RAMB16 symbols being packed together improperly so that this error occurs. If the component name involved is not a RAMB16 component, then this Answer Record is not a good match for your issue.


This error can occur if an unconstrained RAMB16 symbol, driven by a BUFR, is packed into the same RAMB36 component as another RAMB16 symbol that is constrained to a location or range of locations that the BUFR cannot reach. This is an order of processing issue where the packer is not aware of the placement needs of the BUFR domain, and a CR is being investigated to correct the issue.

Meanwhile, rather that setting the environment variable as suggested by the error message, the problem can be avoided by rerunning MAP with the Regional Clock UCF range constraints generated by the first MAP pass. These constraints will block the incorrect packing behavior since the two RAMB16s will now have incompatible constraints.

# Regional-Clock "liw_out_clk" driven by "BUFR_X1Y10"
INST "INC_LIW_DEINT.vxp_out_capture_bufr" LOC = "BUFR_X1Y10" ;
NET "liw_out_clk" TNM_NET = "TN_liw_out_clk" ;
TIMEGRP "TN_liw_out_clk" AREA_GROUP = "CLKAG_liw_out_clk" ;
AR# 25380
Date 12/15/2012
Status Active
Type General Article
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