XAUI v7.1 - Unconnected signals in Virtex-5 Verilog wrappers causes GTP transmitter phase alignment to fail
Description
Keywords: 10, Ten, Gigabit, Ethernet, MAC, known, issues, Virtex-5
Unconnected signals in Virtex-5 Verilog wrappers cause GTP transmitter phase alignment to fail. This is not an issue in the VHDL example design wrapper files and not an issue in the v7.0 or v7.0rev1 versions of the core.
Solution
In the "<core_name>_block.v" file, the TXENPMAPHASEALIGN Output from init block is called mgt_txenpmaphasealign:rocketio_init_tx gtp_init_tx(
.USER_CLK(clk156),
.RESET(reset_txsync),
.SYNC_DONE(mgt_tx_ready),
.TXENPMAPHASEALIGN(mgt_txenpmaphasealign),
.TXPMASETPHASE(mgt_txpmasetphase) );
But on the input to MGT the signal is called mgt_txpmaphasealign. The signal names do not match. Therefore, this input to the MGT is actually not getting driven.This results in the MGT inputs being tied to ground :
.TILE0_TXENPMAPHASEALIGN_IN( mgt_txpmaphasealign),
.TILE1_TXENPMAPHASEALIGN_IN(mgt_txpmaphasealign),
To fix the problem the above will need to be replaced with:
.TILE0_TXENPMAPHASEALIGN_IN(mgt_txenpmaphasealign),
.TILE1_TXENPMAPHASEALIGN_IN(mgt_txenpmaphasealign),