Solution

Issues Addressed in 9.2i Service Packs

ChipScope

(SP2) - (Xilinx Answer 25273) - 9.2i ChipScope - When I insert ChipScope into a project, the CDC file is not displayed in the sources pane of ISE on Windows
(SP4) - (Xilinx Answer 25281) - 9.2i ChipScope Pro Core Inserter - Core Inserter does not open when I double-click the ".cdc" file in ISE

Constraints & Timing

(SP1) - (Xilinx Answer 25192) - Virtex-5 DCM - The DCM does not deskew the clock properly for both system synchronous and source synchronous designs
(SP1) - (Xilinx Answer 25321) - 9.2i Timing Analysis Virtex-5 - IDDR/ODDR are not analyzed for OFFSET IN/OUT constraints with RISING/FALLING timegrps
(SP1) - (Xilinx Answer 25326) - 9.2i Timing Analyzer/trce - "FATAL_ERROR:Timing:bastwoffsetpref.c:646:1.146 - Clock arrival time not found ..."
(SP3) - (Xilinx Answer 29394) - 9.2i MAP/Timing - "FATAL_ERROR:Timing:bastwgraphedit.c:2251:1.36.2.2 ..."
(SP3) - (Xilinx Answer 29395) - 9.2i MAP/TIMING - "FATAL_ERROR:2_196:1.4"
(SP3) - (Xilinx Answer 29396) - 9.2i PAR/TIMING - "FATAL_ERROR:Utilities:UtilIfileimp.c:630:1.15"
(SP3) - (Xilinx Answer 29400) - 9.2i - Timing Analyzer - OFFSET IN analysis had zero items analyzed on IDDR component
(SP3) - (Xilinx Answer 29401) - 9.1i - Timing Analyzer - Timing Report Data Sheet section does not include OFFSET IN Tables
(SP4) - (Xilinx Answer 29884) - 9.2i - Timing Analyzer - "Unexpected Error in Index generation process" error in the timing report
(SP4) - (Xilinx Answer 29882) - 9.2i - Timing Analyzer - Timing Analyzer crashes without producing any error message
(SP4) - (Xilinx Answer 29456) - 9.2i Timing Analyzer - "ERROR: TRACE output file "xrefdes.twr" not found!"
(SP4) - (Xilinx Answer 29901) - 9.1i SP1 Constraints Editor - Unable to find derived clocks
(SP4) - (Xilinx Answer 29883) - 9.2i SP3 Timing - Changes in the calculation of Discrete Jitter for the uncertainty equations for PLL2DCM and DCM2PLL

CORE Generator

(SP1) - (Xilinx Answer 25228) - 9.2i CORE Generator - Generating the Serial RapidIO Core in batch mode causes a segmentation fault
(SP1) - (Xilinx Answer 25229) - 9.2i CORE Generator - PCI cores cannot be generated on WinXP64 or Win 2003: "java.util.zip.ZipException: Not enough disk space in path"
(SP1) - (Xilinx Answer 25230) - 9.1i CORE Generator - Core data sheets fail to open from customization GUI when using Adobe Acrobat 8
(SP1) - (Xilinx Answer 25369) - 9.2i ISE, CORE Generator - Generated core does not appear in ISE project; error message occurs: "CORE Generator generated file <corename>/simulation/glbl.v does not exist in the project directory!"
(SP1) - (Xilinx Answer 25370) - 9.1i CORE Generator - Generation fails if CORE Generator is launched from a directory relative to project directory
(SP2) - (Xilinx Answer 29105) - 9.2i CORE Generator - PCI based IP Cores cannot be generated on Windows Vista

Floorplan Editor

(SP1) - (Xilinx Answer 25323) - 9.2i Floorplan Editor - Input pin termination grayed out
(SP1) - (Xilinx Answer 25324) - 9.2i Floorplanner - "FATAL_ERROR:GuiUtilities:Gq_Application.c:578:1.17"
(SP1) - (Xilinx Answer 25325) - 9.2i Floorplanner - An error occurs when writing DSP48 component LOC constraints
(SP3) - (Xilinx Answer 29397) - 9.2i - PACE/Floorplan Editor - FATAL ERROR after running SSO Analysis
(SP3) - (Xilinx Answer 29398) - 9.2i - PACE/Floorplan Editor/Program File - FATAL ERROR when Floorplan Editor is open and Generate Programming File process is started
(SP3) - (Xilinx Answer 29399) - 9.2i - PACE/Floorplan Editor - FATAL ERROR after launching "Assign Package Pins" process

Install

(SP4) - (Xilinx Answer 29746) - 9.2i SP4 Install - Installation Instructions for Virtex-5 LX20T/LX155/LX155T devices

ISE Text Editor

(SP1) - (Xilinx Answer 23106) - 9.1i ISE Text Editor - East Asian language characters in ISE Text Editor are not displayed
(SP3) - (Xilinx Answer 29307) - 9.2i ISE Text Editor - Asian language characters in ISE Text Editor are deleted when entering a new character
(SP4) - (Xilinx Answer 29853) - 9.2i ISE Text Editor - East Asian language characters in ISE Text Editor appear corrupted after I select save

NGDBuild

(SP1) - (Xilinx Answer 24239) - 9.1i ISE - When implementing a design the following error occurs: "ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "0"

Project Navigator

(SP1) - (Xilinx Answer 25371) - 9.1i ISE - Designs containing IP cores fail to synthesize with either Synplify Pro or Precision
(SP1) - (Xilinx Answer 25372) - 9.1i ISE - Generating specific IP cores through Project -> New Source results in error: "ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "::<core_name>_xmdf::xmdfInit"'
(SP1) - (Xilinx Answer 25375) - 9.1i Tcl - "Xfile add" command with the -copy switch causes Project Navigator to exit abnormally on 64-bit Windows XP
(SP1, SP2, SP3, SP4) - (Xilinx Answer 25378) - 9.2i ISE - Known Issues for Project Navigator 9.2i
(SP2) - (Xilinx Answer 25516) - 9.1i ISE - Project Navigator warning message appears in a pop-up dialog and the GUI becomes unresponsive
(SP3) - (Xilinx Answer 29306) - 9.1i ISE - Project Navigator's Source Control -> Export function lists the ModelSim install directory as a source file
(SP3) - (Xilinx Answer 29043) - 9.2i ISE - In Project Navigator, the Synplify Pro cannot be selected when targeting Spartan-3A DSP
(SP4) - (Xilinx Answer 29431) - 9.2i ISE - Project Navigator fails to create a timing simulation netlist for an EDIF project

Speeds Files

(SP1, SP3) - (Xilinx Answer 23788) - Virtex-5 - Speeds File Revision History
(SP1, SP3) - (Xilinx Answer 24981) - Spartan-3A - Speed File Revision History
(SP3) - (Xilinx Answer 29393) - Spartan-3AN/Spartan-3ADSP - Speed File Revision History

XST

(SP2) - (Xilinx Answer 25289) - 9.1i XST - "ERROR:Xst - CheckCondition - Xst_HdlConst_Utility::ConvertIntegerToType : unable to adjust constant <'S'> (type char) to type enum (0, R, W, S, )."