We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25386

XAUI v7.1 - Updates to Virtex-5 GTP attributes and tx phase alignment procedure


After further Characterization, the Virtex-5 RocketIO GTP Transceiver Users Guide v1.3 and RocketIO GTP Wizard v1.5 have updated attributes and the transmit phase alignment procedure for XAUI. These updates were released after the v7.1 core and will be contained in the next release of the core.


To get the latest attributes and phase alignment procedure, the RocketIO GTP Wizard can be run to generate new rocketio_wrapper.v/.vhd, rocketio_wrapper_tile.v/vhd, and tx_sync.v/vhd files. Use the following steps to replace the original files in the XAUI core example_design directory:

1. Run the RocketIO GTP Wizard in CORE Generator with the correct target device. Leave all of the options as the default, except:

- On page 1, choose the GTPs that will be used. The component name must be rocketio_wrapper, which is the default.

- On page 2 of the RocketIO GTP Wizard, select the following:

silicon: ES or Production

targetline rate: 3.125 Gbps

refclk: 156.25

Check the "Use Dynamic Reconfiguration Port" box

GTP0 protocol template : xaui

GTP1 protocol template: use GTP0 settings

- On page 6 of the Rocket IO GTP Wizard, if the core is not using the IEEE statemachines, select the following:

(If the core is using the IEEE Statemachines, no change is required)

Under RXLOSSOFSYNCPortMeaning select: Loss-of-Sync State Machine status

2. The output will contain the updated files:




Copy these hdl files into the XAUI core example_design directory.

3. tx_sync.v/vhd replaces rocketio_init_tx.v/vhd in the XAUI example_design directory. This means that <xauicore_name>_block.v/vhd must be modified from instantiating rocketio_init_tx to tx_sync.

In VHDL change the line:

gtp_align_tx : rocketio_init_tx


gtp_align_tx : tx_sync

In Verilog, change the line:

rocketio_init_tx gtp_init_tx(


TX_SYNC gtp_init_tx(

3. If using Solaris/Linux, you must edit the rocketio_wrapper.v/vhd file to change the occurrences of ROCKETIO_WRAPPER and ROCKETIO_WRAPPER_TILE from uppercase to lowercase. You can edit the file in a text editor with the Find and Replace function.

AR# 25386
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article