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AR# 25427

Virtex-5 Built-in Endpoint Block for PCI Express - Known Issues and Information not yet available in UG197


This answer record contains known issues and information that will be incorporated into the next revision of UG197. Where appropriate, a work-around is mentioned, along with whether the work-around has been implemented in the Virtex-5 Endpoint Block Plus Wrapper for PCI Express. Information on the Virtex-5 Endpoint Block Plus Wrapper can be found at:



Known Issues Fixed in v1.4 of the Block Plus Wrapper for PCI Express

Item 1

Please see (Xilinx Answer 25473) regarding precautions when using the continuous request mode on the receive data path. The Block Plus Wrapper for PCI Express works around this issue as of the v1.4 release in 9.2i IP Update 1.

Item 2

Please see (Xilinx Answer 29057) regarding the RXPREFFREDTYPE signal going invalid. The Block Plus Wrapper for PCI Express works around this issue as of the v1.3 release initially available in 9.1i IP Update 3.

Known Issues Scheduled To Be Fixed in v1.5 of the Block Plus Wrapper for PCI Express

The v1.5 Block Plus Wrapper will be included with 9.2i IP Update 2 scheduled for release in October 2007.

Item 1

When the host sends an ACK, followed by an electrical idle ordered set to initiate L0s Entry, the integrated block will never see the ACK and instead will replay the packet. If this scenario repeats multiple times, the REPLAY_NUM will roll over, causing the block to initiate link training.

Item 2

According to the PCI Express Specification 2.0, a bit in the TS2 sequence is used as a Link Upconfigure bit. This bit is reserved in PCI Express Specification 1.1. The integrated block is expected to transmit a "1" on the bit and ignore the value on the RX side. The integrated block does not ignore this bit and fails to link train if it is set to 1.

AR# 25427
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article